T89C51CC02UA-SISIM Atmel, T89C51CC02UA-SISIM Datasheet - Page 100
![IC 8051 MCU FLASH 16K 28PLCC](/photos/6/70/67044/453-28-plcc_sml.jpg)
T89C51CC02UA-SISIM
Manufacturer Part Number
T89C51CC02UA-SISIM
Description
IC 8051 MCU FLASH 16K 28PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.T89C51CC02CA-TDSIM.pdf
(159 pages)
2.T89C51CC02CA-TDSIM.pdf
(33 pages)
3.T89C51CC02CA-TDSIM.pdf
(29 pages)
4.T89C51CC02CA-TDSIM.pdf
(148 pages)
Specifications of T89C51CC02UA-SISIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-PLCC
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC02UASISIM
Available stocks
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Manufacturer
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AT/T89C51CC02
Table 64. CANIE Register
CANIE (S:C3h) – CAN Enable Interrupt message object Registers
Reset Value = xxxx 0000b
Table 65. CANBT1 Register
CANBT1 (S:B4h) – CAN bit Timing Registers 1
Note:
No default value after reset.
Bit Number
Bit Number
7
7
-
-
7 - 4
3 - 0
6 - 1
7
0
1. The CAN controller bit timing registers must be accessed only if the CAN controller is
disabled with the ENA bit of the CANGCON register set to 0.
See Figure 41.
BRP 5
6
6
-
Bit Mnemonic
Bit Mnemonic
IECH3:0
BRP5:0
-
-
-
BRP 4
5
5
-
Description
Reserved
The values read from these bits are indeterminate. Do not set these
bits.
Enable Interrupt by Message Object
0 - disable IT.
1 - enable IT.
IECH3:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 & 2.
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud Rate Prescaler
The period of the CAN controller system clock Tscl is
programmable and determines the individual bit timing.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
BRP 3
4
4
-
IECH 3
BRP 2
3
3
Tscl =
BRP[5..0] + 1
IECH 2
BRP 1
F
CAN
2
2
IECH 1
BRP 0
1
1
4126L–CAN–01/08
(1)
IECH 0
0
0
-
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