ATMEGA48V-10MI Atmel, ATMEGA48V-10MI Datasheet - Page 205
ATMEGA48V-10MI
Manufacturer Part Number
ATMEGA48V-10MI
Description
IC AVR MCU 4K 5V 12MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA48V-10MI
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA48V-12MI
ATMEGA48V-12MI
ATMEGA48V-12MI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48V-10MI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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20.8
20.8.1
20.8.2
20.8.3
2545S–AVR–07/10
Register Description
UDRn – USART MSPIM I/O Data Register
UCSRnA – USART MSPIM Control and Status Register n A
UCSRnB – USART MSPIM Control and Status Register n B
The following section describes the registers used for SPI operation using the USART.
The function and bit description of the USART data register (UDRn) in MSPI mode is identical to
normal USART operation. See “UDRn – USART I/O Data Register n” on page 189.
• Bit 7 - RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (that is, does not contain any unread data). If the Receiver is disabled, the
receive buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag
can be used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
• Bit 6 - TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCIEn bit).
• Bit 5 - UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to
indicate that the Transmitter is ready.
• Bit 4:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnA is written.
• Bit 7 - RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the RXCn bit in UCSRnA is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
RXCn
R
7
0
RXCIEn
R/W
7
0
TXCn
R/W
6
0
TXCIEn
R/W
6
0
UDREn
R
5
0
UDRIE
R/W
5
0
R
4
0
-
RXENn
R/W
4
0
R
3
0
-
TXENn
R/W
3
0
R
2
1
-
ATmega48/88/168
R
2
1
-
R
1
1
-
R
1
1
-
R
0
0
-
R
0
0
-
UCSRnB
UCSRnA
205
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