ATMEGA88-20PJ Atmel, ATMEGA88-20PJ Datasheet - Page 75

IC MCU AVR 8K 5V 20MHZ 28-DIP

ATMEGA88-20PJ

Manufacturer Part Number
ATMEGA88-20PJ
Description
IC MCU AVR 8K 5V 20MHZ 28-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88-20PJ

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA88-24PJ
ATMEGA88-24PJ
13.3
2545S–AVR–07/10
Alternate Port Functions
ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins
directly to V
accidentally configured as an output.
Most port pins have alternate functions in addition to being general digital I/Os.
shows how the port pin control signals from the simplified
alternate functions. The overriding signals may not be present in all port pins, but the figure
serves as a generic description applicable to all port pins in the AVR microcontroller family.
Figure 13-5. Alternate Port Functions
Note:
PTOExn:
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
CC
Pxn PULL-UP OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
SLEEP CONTROL
Pxn, PORT TOGGLE OVERRIDE ENABLE
or GND is not recommended, since this may cause excessive currents if the pin is
1
0
1
0
1
0
1
0
PUOExn
PUOVxn
DIEOExn
DDOExn
DDOVxn
PVOExn
PVOVxn
DIEOVxn
SLEEP
(1)
PUD:
WDx:
RDx:
RRx:
WRx:
RPx:
WPx:
clk
DIxn:
AIOxn:
SYNCHRONIZER
D
L
I/O
SET
CLR
:
Q
Q
WRITE DDRx
WRITE PORTx
PULLUP DISABLE
READ DDRx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
D
PINxn
CLR
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
Figure 13-2
D
D
ATmega48/88/168
1
0
clk
PUD
WDx
RRx
DIxn
AIOxn
RDx
RPx
I/O
WRx
can be overridden by
PTOExn
WPx
Figure 13-5
I/O
,
75

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