AT90CAN128-16AI Atmel, AT90CAN128-16AI Datasheet - Page 186
![IC MCU AVR FLASH 128K 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT90CAN128-16AI
Manufacturer Part Number
AT90CAN128-16AI
Description
IC MCU AVR FLASH 128K 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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17.7.4
17.7.5
17.8
17.8.1
186
Data Reception – USART Receiver
AT90CAN32/64/128
Parity Generator
Disabling the Transmitter
Receiving Frames with 5 to 8 Data Bits
The Data Register Empty (UDREn) flag indicates whether the transmit buffer is ready to receive
new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer
contains data to be transmitted that has not yet been moved into the Shift Register. For compat-
ibility with future devices, always write this bit to zero when writing the UCSRnA Register.
When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRBn is written to one, the
USARTn Data Register Empty Interrupt will be executed as long as UDREn is set (provided that
global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data
transmission is used, the Data Register Empty interrupt routine must either write new data to
UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new
interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXCn) flag bit is set one when the entire frame in the Transmit Shift
Register has been shifted out and there are no new data currently present in the transmit buffer.
The TXCn flag bit is automatically cleared when a transmit complete interrupt is executed, or it
can be cleared by writing a one to its bit location. The TXCn flag is useful in half-duplex commu-
nication interfaces (like the RS-485 standard), where a transmitting application must enter
receive mode and free the communication bus immediately after completing the transmission.
When the Transmit Complete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USARTn
Transmit Complete Interrupt will be executed when the TXCn flag becomes set (provided that
global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-
dling routine does not have to clear the TXCn flag, this is done automatically when the interrupt
is executed.
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled
(UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the
first stop bit of the frame that is sent.
The disabling of the Transmitter (setting the TXENn to zero) will not become effective until ongo-
ing and pending transmissions are completed, i.e., when the Transmit Shift Register and
Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter
will no longer override the TxDn pin.
The USARTn Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCSRnB
Register to one. When the Receiver is enabled, the normal pin operation of the RxDn pin is over-
ridden by the USARTn and given the function as the Receiver’s serial input. The baud rate,
mode of operation and frame format must be set up once before any serial reception can be
done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer clock.
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start
bit will be sampled at the baud rate or XCKn clock, and shifted into the Receive Shift Register
until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver.
When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift
Register, the contents of the Shift Register will be moved into the receive buffer. The receive
buffer can then be read by reading the UDRn I/O location.
7679H–CAN–08/08
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