TSC80251G2D-16CB Atmel, TSC80251G2D-16CB Datasheet
TSC80251G2D-16CB
Specifications of TSC80251G2D-16CB
Available stocks
Related parts for TSC80251G2D-16CB
TSC80251G2D-16CB Summary of contents
Page 1
... TSC87251G2D: 32 kilobytes of On-Chip EPROM/OTPROM – SINGLE PULSE Programming Algorithm • TSC83251G2D: 32 kilobytes of On-Chip Masked ROM • TSC80251G2D: ROMless Version • Four 8-bit Parallel I/O Ports (Ports and 3 of the Standard 80C51) • Serial I/O Port: Full Duplex UART (80C51 Compatible) With Independent Baud Rate Generator • ...
Page 2
... TSC80251G2D derivatives are optimized for speed and for low power consumption on a wide voltage range. Note: 1. This Datasheet provides the technical description of the TSC80251G2D derivatives. For further information on the device usage, please request the TSC80251 Programmer’s Guide and the TSC80251G1D Design Guide and errata sheet. ...
Page 3
Block Diagram P3(A16) P2(A15-8) PSEN# PORTS 0-3 ALE/PROG# EA#/VPP AWAIT# Bus Interface Unit VDD VSS 4135F–8051–11/06 P1(A17) P0(AD7-0) ROM EPROM RAM OTPROM 1 Kbyte 32 KB 16-bit Memory Code 16-bit Memory Address CPU VSS1 VSS2 AT/TSC8x251G2D Timers 0, 1 and ...
Page 4
... Pin Description Figure 1. TSC80251G2D 40-pin DIP package Pinout Figure 2. TSC80251G2D 44-pin PLCC Package AT/TSC8x251G2D 4 P1.0/T2 1 P1.1/T2EX 2 P1.2/ECI 3 P1.3/CEX0 4 P1.4/CEX1/SS# 5 P1.5/CEX2/MISO 6 P1.6/CEX3/SCL/SCK/WAIT# 7 P1.7/A17/CEX4/SDA/MOSI/WCLK 8 RST 9 P3.0/RXD 10 P3.1/TXD 11 P3.2/INT0# 12 P3.3/INT1# 13 P3.4/T0 14 P3.5/T1 15 P3.6/WR# 16 P3.7/A16/RD# 17 XTAL2 18 XTAL1 19 VSS 20 P1.5/CEX2/MISO 7 P1.6/CEX3/SCL/SCK/WAIT# 8 P1.7/A17/CEX4/SDA/MOSI/WCLK 9 RST 10 P3.0/RXD 11 AWAIT# 12 P3.1/TXD 13 P3 ...
Page 5
... Figure 3. TSC80251G2D 44-pin VQFP Package 4135F–8051–11/06 P1.5/CEX2/MISO 1 P1.6/CEX3/SCL/SCK/WAIT# 2 P1.7/A17/CEX4/SDA/MOSI/WCLK 3 RST 4 P3.0/RXD 5 AWAIT# 6 P3.1/TXD 7 P3.2/INT0# 8 P3.3/INT1# 9 P3.4/T0 10 P3.5/T1 11 AT/TSC8x251G2D 33 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 EA#/VPP TSC80251G2D 28 NMI 27 ALE/PROG# 26 PSEN# 25 P2.7/A15 24 P2.6/A14 23 P2.5/A13 5 ...
Page 6
... Table 1. TSC80251G2D Pin Assignment DIP PLCC VQFP Name 1 39 VSS1 P1.0/ P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1/SS P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD 12 6 AWAIT P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/ P3.5/ P3.6/WR P3.7/A16/RD XTAL2 XTAL1 VSS AT/TSC8x251G2D 6 DIP PLCC VQFP Name 23 17 VSS2 P2.0/ P2.1/A9 ...
Page 7
Signals Table 2. Product Name Signal Description 4135F–8051–11/06 Signal Name Type Description th 18 Address Bit Output to memory as 18th external address bit (A17) in extended bus A17 O applications, depending on the values of bits RD0 and RD1 ...
Page 8
Table 2. Product Name Signal Description (Continued) AT/TSC8x251G2D 8 Signal Name Type Description Non Maskable Interrupt Holding this pin high for 24 oscillator periods triggers an interrupt. When using the Product Name as a pin-for-pin replacement for a 8xC51 NMI ...
Page 9
... This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. VSS2 GND However, when using the TSC80251G2D as a pin-for-pin replacement for a 8xC51 product, VSS2 can be unconnected without loss of compatibility. Not available on DIP package. Real-time Synchronous Wait States Input ...
Page 10
Table 2. Product Name Signal Description (Continued) Note: AT/TSC8x251G2D 10 Signal Name Type Description Output of the on-chip inverting oscillator amplifier XTAL2 O To use the internal oscillator, a crystal/resonator circuit is connected to this pin external oscillator ...
Page 11
... The TSC83251G2D products provide the internal program/code memory in a masked ROM memory while the TSC87251G2D products provide EPROM memory. For the TSC80251G2D products, there is no internal program/code memory and EA# must be tied to a low level. Figure 4. Program/Code Memory Mapping Note: 4135F– ...
Page 12
... On-Chip Code Memory Map configuration bit is cleared (EMAP# bit in UCONFIG1 byte, see Figure ). However, if EA# is tied to a low level, the TSC80251G2D derivative is running as a ROMless product and the code is actually fetched in the corresponding external memory (i.e. the upper the lower the segment FF:) ...
Page 13
... The Special Function Registers (SFRs) of the TSC80251G2D derivatives fall into the Special Function categories detailed in Table 1 to Table 9. Registers SFRs are placed in a reserved on-chip memory region S: which is not represented in the data memory mapping (Figure 5). The relative addresses within S: of these SFRs are provided together with their reset values in Table . They are upward compatible with the SFRs of the standard 80C51 and the Intel’ ...
Page 14
Table 4. Serial I/O Port SFRs Table 5. SSLC SFRs Table 6. Event Waveform Control SFRs Mnemonic Name AT/TSC8x251G2D 14 Mnemonic Name SCON Serial Control SBUF Serial Data Buffer Slave Address SADEN Mask Mnemonic Name Synchronous Serial SSCON control Synchronous ...
Page 15
Table 7. System Management SFRs Mnemonic Name PCON POWM Table 8. Interrupt SFRs Mnemonic Name IE0 IE1 IPH0 Table 9. Keyboard Interface SFRs Mnemonic Name P1IE P1F 4135F–8051–11/06 Power Control CKRL Power Management WCON Interrupt Enable Control 0 IPL0 Interrupt ...
Page 16
Table 10. SFR Descriptions 0/8 1/9 CH F8h 0000 0000 (1) B F0h 0000 0000 CL E8h 0000 0000 (1) ACC E0h 0000 0000 CCON CMOD D8h 00X0 0000 00XX X000 (1) (1) PSW PSW1 D0h 0000 0000 0000 0000 ...
Page 17
... When EA# is tied to a low level, the configuration bytes are fetched from the external address space. The TSC80251G2D derivatives reserve the top eight bytes of the mem- ory address space (FF:FFF8h-FF:FFFFh) for an external 8-byte configuration array. Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1 at FF:FFF9h ...
Page 18
Table 11. Configuration Byte 0 UCONFIG0 Bit Number Notes: AT/TSC8x251G2D WSA1# WSA0# XALE# Bit Mnemonic Description Reserved 7 - Set this bit when writing to UCONFIG0. 6 WSA1# Wait State A bits Select the ...
Page 19
... Bit Mnemonic Description On-Chip Code Memory Size bit CSIZE Clear to select on-chip code memory (TSC87251G1D TSC87251G2D product). 7 Set to select on-chip code memory (TSC87251G2D product). TSC80251G2D Reserved TSC83251G2D Set this bit when writing to UCONFIG1. Reserved 6 - Set this bit when writing to UCONFIG1. Reserved ...
Page 20
Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals Configuration Byte 1 Notes: AT/TSC8x251G2D 20 RD1 RD0 P1.7 P3.7/RD A17 A16 0 1 I/O pin A16 1 0 I/O pin I/O pin Read signal for ...
Page 21
Instruction Set This section contains tables that summarize the instruction set. For each instruction there is a short description, its length in bytes, and its execution time in states (one state Summary time is equal to two system clock cycles). ...
Page 22
Table 16. Notation for Immediate Addressing #data #data16 #0data16 #1data16 #short Table 17. Notation for Bit Addressing bit51 bit Table 18. Notation for Destination in Control Instructions rel addr11 addr16 addr24 AT/TSC8x251G2D 22 Immediate Address Description An 8-bit constant that ...
Page 23
Table 19. Notation for Register Operands Rmd Rms m, md, ms WRj WRjd WRjs at WRj at WRj +dis16 j, jd, js DRk DRkd DRks at DRk at DRk +dis16 k, kd, ks 4135F–8051–11/06 Register ...
Page 24
Table 20. Summary of Add and Subtract Instructions Size and Execution Time for Instruction Families AddADD <dest>, <src>dest opnd ← dest opnd + src opnd SubtractSUB <dest>, <src>dest opnd ← dest opnd - src opnd Add with CarryADDC <dest>, <src>(A) ...
Page 25
Table 21. Summary of Increment and Decrement Instructions IncrementINC <dest>dest opnd ← dest opnd + 1 IncrementINC <dest>, <src>dest opnd ← dest opnd + src opnd DecrementDEC <dest>dest opnd ← dest opnd - 1 DecrementDEC <dest>, <src>dest opnd ← dest ...
Page 26
Table 22. Summary of Compare Instructions CompareCMP <dest>, <src>dest opnd - src opnd Mnemonic CMP Notes: AT/TSC8x251G2D 26 <dest>, (2) <src> Comments Rmd, Rms Register with register WRjd, Word register with word register WRjs DRkd, Dword register with dword register ...
Page 27
ANL <dest>, <src>dest opnd ← dest opnd Λ src opnd Logical AND (1) Logical OR ORL <dest>, <src>dest opnd ← dest opnd ς src opnd (1) Logical Exclusive OR XRL <dest>, <src>dest opnd ← dest opnd ∀ src opnd ...
Page 28
Notes: 1. Logical instructions that affect a bit are in Table 27 shaded cell denotes an instruction in the C51 Architecture this instruction addresses an I/O Port (Px 0-3), add 1 to the number ...
Page 29
Table 24. Summary of Multiply, Divide and Decimal-adjust Instructions MultiplyMUL AB(B:A) ← (A)×(B) MUL <dest>, <src>extended dest opnd ← dest opnd × src opnd DivideDIV AB(A) ← Quotient ((A) ⁄ (B)) DivideDIV <dest>, <src>ext. dest opnd high ← Quotient (dest ...
Page 30
Table 25. Summary of Move Instructions (1/3) Move to High wordMOVH <dest>, <src>dest opnd Move with Sign extensionMOVS <dest>, <src>dest opnd ← src opnd with sign extend Move with Zero extensionMOVZ <dest>, <src>dest opnd ← src opnd with zero extend ...
Page 31
Table 26. Summary of Move Instructions (2/3) Move Mnemonic MOV Notes: 4135F–8051–11/06 (1) MOV <dest>, <src>dest opnd ← src opnd <dest>, (2) <src> Comments A, Rn Register to ACC Direct address (on-chip RAM or SFR) A, dir8 to ACC A, ...
Page 32
Move MOV <dest>, <src>dest opnd ← src opnd (1) Mnemonic <dest>, <src> Comments MOV Rmd, Rms Byte register to byte register MOV WRjd, WRjs Word register to word register MOV DRkd, DRks Dword register to dword register MOV Rm, ...
Page 33
WRj, at WRj MOV Indirect with 16-bit displacement (16M) to word register +dis24 at WRj +dis16, MOV Byte register to indirect with 16-bit displacement (64K WRj +dis16, MOV Word register to indirect with 16-bit displacement (64K) WRj at ...
Page 34
Table 27. Summary of Bit Instructions Clear BitCLR <dest>dest opnd ← 0 Set BitSETB <dest>dest opnd ← 1 Complement BitCPL <dest>dest opnd ← ∅ bit AND Carry with BitANL CY, <src>(CY) ← (CY) ∧ src opnd AND Carry with Complement ...
Page 35
Table 28. Summary of Exchange, Push and Pop Instructions Exchange bytesXCH A, <src>(A) ↔ src opnd Exchange DigitXCHD A, <src>(A) PushPUSH <src>(SP) ← (SP) +1; ((SP)) ← src opnd; PopPOP <dest>(SP) ← (SP) - size (dest opnd Mnemonic ...
Page 36
Table 29. Summary of Conditional Jump Instructions (1/2) Jump conditional on statusJcc rel(PC) ← (PC) + size (instr); Mnemonic JC JNC JE JNE JG JLE JSL JSLE JSG JSGE Notes: AT/TSC8x251G2D 36 IF [cc] THEN (PC) ← (PC) + rel ...
Page 37
Table 30. Summary of Conditional Jump Instructions (2/2) Jump if bitJB <src>, rel(PC) ← (PC) + size (instr); Jump if not bitJNB <src>, rel(PC) ← (PC) + size (instr); Jump if bit and clearJBC <dest>, rel(PC) ← (PC) + size ...
Page 38
Table 31. Summary of Unconditional Jump Instructions Absolute jumpAJMP <src>(PC) ← (PC) +2; (PC) Extended jumpEJMP <src>(PC) ← (PC) + size (instr); (PC) Long jumpLJMP <src>(PC) ← (PC) + size (instr); (PC) Short jumpSJMP rel(PC) ← (PC) +2; (PC) ← ...
Page 39
Table 32. Summary of Call and Return Instructions Absolute callACALL <src>(PC) ← (PC) +2; push (PC) Extended callECALL <src>(PC) ← (PC) + size (instr); push (PC) Long callLCALL <src>(PC) ← (PC) + size (instr); push (PC) Return from subroutineRETpop (PC) ...
Page 40
... Mask ROM Devices cells. They can only be verified by the user, using the same algorithm as the EPROM/OTPROM devices. The TSC80251G2D products do not include on-chip Configuration Bytes, Code Memory ROMless Devices and Encryption Array. They only include Signature Bytes made of Mask ROM cells which can be read using the same algorithm as the EPROM/OTPROM devices ...
Page 41
The TSC87251G2D products implement 3 levels of security for User’s program as Lock Bit System described in Table 33. The TSC83251G2D products implement only the first level of security. Level 0 is the level of an erased part and does ...
Page 42
... To preserve the secrecy of the encryption key byte sequence, the Encryption Array can not be verified. Notes: The TSC80251G2D derivatives contain factory-programmed Signature Bytes. These Signature Bytes bytes are located in non-volatile memory outside the memory address space at 30h, 31h, 60h and 61h. To read the Signature Bytes, perform the procedure described in sec- tion Verify Algorithm, using the verify signature mode (see Table 37) ...
Page 43
Figure 6. Setup for Programming Table 36. Programming Modes ROM Area On-chip Code Memory Configuration Bytes Lock Bits Encryption Array Notes ...
Page 44
Table 37. Verifying Modes ROM Area On-chip code memory Configuration Bytes Lock Bits Signature Bytes Notes: Figure 7. Setup for Verifying AT/TSC8x251G2D 44 Then device is driving the data on Port possible to alternate ...
Page 45
... Test conditions: capacitive load on all pins = 50 pF. Timings Table 39 and Table 40 list the AC timing parameters for the TSC80251G2D derivatives with no wait states. External wait states can be added by extending PSEN#/RD#/WR# and or by extending ALE. In these tables, Note 2 marks parameters affected by one ALE wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states ...
Page 46
Table 39. Bus Cycles AC Timings; V Symbol Notes: AT/TSC8x251G2D 46 DD Parameter T 1/F OSC OSC T ALE Pulse Width LHLL T Address Valid to ALE Low AVLL T Address hold after ALE Low LLAX (1) T RD#/PSEN# Pulse ...
Page 47
Table 40. Bus Cycles AC Timings; V Notes: 4135F–8051–11/06 Symbol Parameter T 1/F OSC OSC T ALE Pulse Width LHLL T Address Valid to ALE Low AVLL T Address hold after ALE Low LLAX (1) T RD#/PSEN# Pulse Width RLRH ...
Page 48
Waveforms in Non-Page Mode Figure 8. External Bus Cycle: Code Fetch (Non-Page Mode) Note: Figure 9. External Bus Cycle: Data Read (Non-Page Mode) Note: AT/TSC8x251G2D 48 ALE TLHLL(1) PSEN P2/A16/A17 1. The value of this parameter depends on ...
Page 49
Figure 10. External Bus Cycle: Data Write (Non-Page Mode) Note: Figure 11. External Bus Cycle: Code Fetch (Page Mode) Waveforms in Page Mode Note: 4135F–8051–11/06 ALE TLHLL(1) WR# (1) T LHAX TAVLL(1) T LLAX A7:0 P0 (1) T AVWL1 (1) ...
Page 50
Figure 12. External Bus Cycle: Data Read (Page Mode) Note: Figure 13. External Bus Cycle: Data Write (Page Mode) Note: AC Characteristics - Real-Time Synchronous Wait State Table 41. Real-Time Synchronous Wait Timing Symbol Definitions Definition of Symbols AT/TSC8x251G2D 50 ...
Page 51
Table 42. Real-Time Synchronous Wait AC Timings; V Timings 85°C Waveforms Figure 14. Real-time Synchronous Wait State: Code Fetch/Data Read State 1 WCLK ALE RD#/PSEN# WAIT Figure 15. Real-time Synchronous Wait State: Data Write State 1 WCLK ALE ...
Page 52
AC Characteristics - Real-Time Asynchronous Wait State Table 43. Real-Time Asynchronous Wait Timing Symbol Definitions Definition of Symbols S Y Table 44. Real-Time Asynchronous Wait AC Timings; V Timings 85°C Note: Figure 16. Real-time Asynchronous Wait State Timings Waveforms AC ...
Page 53
Table 46. Serial Port AC Timing -Shift Register Mode; V Timings 85°C Note: Waveforms Figure 17. Serial Port Waveforms - Shift Register Mode T XLXL TXD T QVXH T XHQX RXD (Out XHDV RXD (In) Valid Valid ...
Page 54
AC Characteristics - SSLC: TWI Interface Table 47. TWI Interface AC Timing; V Timings Notes: Waveforms Figure 18. TWI Waveforms START or Repeated START condition SDA (INPUT/OUTPUT SCL (INPUT/OUTPUT) T ;STA HD AT/TSC8x251G2D 54 Symbol Parameter T ; ...
Page 55
AC Characteristics - SSLC: SPI Interface Table 48. SPI Interface Timing Symbol Definitions Definition of Symbols 4135F–8051–11/06 Signals C Clock I Data In O Data Out S SS# AT/TSC8x251G2D Conditions H High L Low V Valid X No Longer Valid ...
Page 56
Table 49. SPI Interface AC Timing; V Timings Notes: AT/TSC8x251G2D 56 ...
Page 57
Figure 19. SPI Master Waveforms (SSCPHA = 0) Waveforms (1) SS# (output) SCK (SSCPOL = 0) (output) SCK (SSCPOL = 1) (output) MISO (input) MOSI Port Data (output) Note: 1. SS# handled by software. Figure 20. SPI Master Waveforms (SSCPHA ...
Page 58
Figure 21. SPI Slave Waveforms (SSCPHA = 0) SS# (input) SCK (SSCPOL = 0) (input) SCK (SSCPOL = 1) (input) MISO (output) MOSI (input) Note: 1. Not Defined but generally the LSB of the character which has just been received. ...
Page 59
Table 51. EPROM Programming AC timings; V Timings Table 52. EPROM Verifying AC timings; V 40°C Waveforms Figure 23. EPROM Programming Waveforms P1 = A15 A7 D7 EA#/VPP ALE/PROG# P0 ...
Page 60
Figure 24. EPROM Verifying Waveforms P1 = A15 A7 D7 Characteristics - External Clock Drive and Logic Level References Table 53. External Clock Timing Symbol Definitions Definition of Symbols Table 54. External Clock AC ...
Page 61
Figure 26. AC Testing Input/Output Waveforms Note: Figure 27. Float Waveforms 4135F–8051–11/06 INPUTS V - 0 0 0.1 DD 0.45 V For timing purposes, a port pin is no longer floating when ...
Page 62
Absolute Maximum Rating and Operating Conditions Absolute Maximum Ratings Storage Temperature ......................................... -65 to +150°C Voltage on any other Pin to VSS ........................ -0 per I/O Pin ................................................................ Power Dissipation ........................................................... 1.5 W ...
Page 63
DC Characteristics High Speed Versions - Commercial, Industrial, and Automotive Table 55. DC Characteristics 4 Symbol Parameter Input Low Voltage V IL (except EA#, SCL, SDA) Input Low Voltage (5) V IL1 (SCL, ...
Page 64
Notes: 1. Under steady-state (non-transient) conditions, I Maximum IOL per port pin Maximum IOL per 8-bit port:Port Ports 1 Maximum Total IOL for all: Output Pins IOL exceeds the test ...
Page 65
Low Voltage Versions - Commercial & Industrial Table 56. DC Characteristics 2 Symbol Parameter Input Low Voltage V IL (except EA#, SCL, SDA) Input Low Voltage (5) V IL1 (SCL, SDA) Input Low ...
Page 66
... Active mode (mA) Frequency at XTAL(1) (MHz) typ Active mode (mA) max Idle mode (mA) typ Idle mode (mA) 1.The clock prescaler is not used: F Test Condition, Active Mode DD VDD RST TSC80251G2D (NC) XTAL2 Clock Signal XTAL1 VSS All other pins are unconnected will be recog 2.7 to 3.6 V ...
Page 67
... Test Condition, Idle Mode DL RST TSC80251G2D (NC) XTAL2 Clock Signal XTAL1 VSS All other pins are unconnected Test Condition, Power-Down Mode PD RST TSC80251G2D (NC) XTAL2 XTAL1 VSS All other pins are unconnected AT/TSC8x251G2D VDD IDL VDD VDD P0 EA# VDD IPD ...
Page 68
Packages • List of Packages • • • • Figure 33. Plastic Dual In Line PDIL 40 - Mechanical Outline Table 57. PDIL Package Size AT/TSC8x251G2D 68 PDIL 40 CDIL 40 with window PLCC 44 CQPJ 44 with window VQFP ...
Page 69
Figure 34. Ceramic Dual In Line CDIL 40 with Window - Mechanical Outline Table 58. CDIL Package Size 4135F–8051–11/06 MM Min Max A - 5.71 b 0.36 0.58 b2 1.14 1.65 c 0.20 0. 53.47 E 13.06 15.37 ...
Page 70
Figure 35. Plastic Lead Chip Carrier PLCC 44 - Mechanical Outline Table 59. PLCC Package Size AT/TSC8x251G2D 70 MM Min Max A 4.20 4.57 A1 2.29 3.04 D 17.40 17.65 D1 16.44 16.66 D2 14.99 16.00 E 17.40 17.65 E1 ...
Page 71
Figure 36. Ceramic Quad Pack J CQPJ 44 with Window - Mechanical Outline Table 60. CQPJ Package Size 4135F–8051–11/06 MM Min 0. 17. 16.36 e 1.27 TYP f 0.43 J 0.86 ...
Page 72
Figure 37. Shrink Quad Flat Pack (Plastic) VQFP 44 (10x10) - Mechanical Outline Table 61. VQFP Package Size AT/TSC8x251G2D 72 MM Min Max A - 1.60 A1 0.64 REF A2 0.64 REF A3 1.35 1.45 D 11.90 12.10 D1 9.90 ...
Page 73
... Ordering Information AT/TSC80251G2D ROMless TSC80251G2D-16CB TSC80251G2D-24CB TSC80251G2D-24CE TSC80251G2D-24IA TSC80251G2D-24IB AT80251G2D-SLSUM AT80251G2D-3CSUM AT80251G2D-RLTUM TSC80251G2D-L16CB TSC80251G2D-L16CE AT80251G2D-SLSUL AT80251G2D-RLTUL AT/TSC83251G2D 32 kilobytes MaskROM TSC251G2Dxxx-16CB TSC251G2Dxxx-24CB TSC251G2Dxxx-24CE TSC251G2Dxxx-24IA TSC251G2Dxxx-24IB AT251G2Dxxx-SLSUM AT251G2Dxxx-3CSUM AT251G2Dxxx-RLTUM AT251G2Dxxx-SLSTM 4135F–8051–11/06 Part Number ROM High Speed Versions 4.5 to 5.5 V, Commercial and Industrial ...
Page 74
TSC251G2Dxxx-L16CB TSC251G2Dxxx-L16CE AT251G2Dxxx-SLSUL AT251G2Dxxx-RLTUL Note: 1. xxx: means ROM code, is Cxxx in case of encrypted code. AT/TSC8x251G2D 74 (1) Part Number ROM Description Low Voltage Versions 2.7 to 5.5 V 32K MaskROM 16 MHz, Commercial 0° to 70°C, PLCC ...
Page 75
AT/TSC87251G2D OTPROM TSC87251G2D-16CB TSC87251G2D-24CB TSC87251G2D-24CED TSC87251G2D-24IA TSC87251G2D-24IB AT87251G2D-SLSUM AT87251G2D-3CSUM AT87251G2D-RLTUM TSC87251G2D-L16CB TSC87251G2D-L16CED AT87251G2D-SLSUL AT87251G2D-RLTUL Document Revision History 1. Added automotive qualification, and ordering information for ROM product version. Changes from 4135D to 4135E Changes from 1. Absolute Maximum Ratings added ...
Page 76
... ROM code encryption Options (Please • Tape & Reel or Dry Pack consult Atmel sales) • Known good dice • Extended temperature range: -55°C to +125°C Product Markings AT/TSC8x251G2D 76 ROMless versions Mask ROM versions ATMEL ATMEL Part number Customer Part number Part Number YYWW ...
Page 77
... Atmel does not make any commitment to update the information contained herein. Unless specifically providedot- herwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as compo- nents in applications intended to support or sustain life. © ...