TSC87251G2D-24IB Atmel, TSC87251G2D-24IB Datasheet
TSC87251G2D-24IB
Specifications of TSC87251G2D-24IB
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TSC87251G2D-24IB Summary of contents
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... Linear Addressing • 1 Kbyte of On-Chip RAM • External Memory Space (Code/Data) Programmable from 64 kilobytes to 256 kilobytes • TSC87251G2D: 32 kilobytes of On-Chip EPROM/OTPROM – SINGLE PULSE Programming Algorithm • TSC83251G2D: 32 kilobytes of On-Chip Masked ROM • TSC80251G2D: ROMless Version • Four 8-bit Parallel I/O Ports (Ports and 3 of the Standard 80C51) • ...
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... Kbyte RAM) and up to 256 kilobytes of external code and data. Additionally, the TSC83251G2D and TSC87251G2D provide on-chip code memory: 32 kilobytes ROM and 32 kilobytes EPROM/OTPROM respectively. They provide transparent enhancements to Intel’s 8xC251Sx family with an additional Synchronous Serial Link Controller (SSLC supporting TWI, μ ...
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Block Diagram P3(A16) P2(A15-8) PSEN# PORTS 0-3 ALE/PROG# EA#/VPP AWAIT# Bus Interface Unit VDD VSS 4135F–8051–11/06 P1(A17) P0(AD7-0) ROM EPROM RAM OTPROM 1 Kbyte 32 KB 16-bit Memory Code 16-bit Memory Address CPU VSS1 VSS2 AT/TSC8x251G2D Timers 0, 1 and ...
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Pin Description Figure 1. TSC80251G2D 40-pin DIP package Pinout Figure 2. TSC80251G2D 44-pin PLCC Package AT/TSC8x251G2D 4 P1.0/T2 1 P1.1/T2EX 2 P1.2/ECI 3 P1.3/CEX0 4 P1.4/CEX1/SS# 5 P1.5/CEX2/MISO 6 P1.6/CEX3/SCL/SCK/WAIT# 7 P1.7/A17/CEX4/SDA/MOSI/WCLK 8 RST 9 P3.0/RXD 10 P3.1/TXD 11 P3.2/INT0# ...
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Figure 3. TSC80251G2D 44-pin VQFP Package 4135F–8051–11/06 P1.5/CEX2/MISO 1 P1.6/CEX3/SCL/SCK/WAIT# 2 P1.7/A17/CEX4/SDA/MOSI/WCLK 3 RST 4 P3.0/RXD 5 AWAIT# 6 P3.1/TXD 7 P3.2/INT0# 8 P3.3/INT1# 9 P3.4/T0 10 P3.5/T1 11 AT/TSC8x251G2D 33 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 EA#/VPP ...
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Table 1. TSC80251G2D Pin Assignment DIP PLCC VQFP Name 1 39 VSS1 P1.0/ P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1/SS P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# ...
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Signals Table 2. Product Name Signal Description 4135F–8051–11/06 Signal Name Type Description th 18 Address Bit Output to memory as 18th external address bit (A17) in extended bus A17 O applications, depending on the values of bits RD0 and RD1 ...
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Table 2. Product Name Signal Description (Continued) AT/TSC8x251G2D 8 Signal Name Type Description Non Maskable Interrupt Holding this pin high for 24 oscillator periods triggers an interrupt. When using the Product Name as a pin-for-pin replacement for a 8xC51 NMI ...
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Table 2. Product Name Signal Description (Continued) 4135F–8051–11/06 Signal Name Type Description Timer 1:0 External Clock Inputs T1:0 I/O When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. Timer 2 Clock Input/Output ...
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Table 2. Product Name Signal Description (Continued) Note: AT/TSC8x251G2D 10 Signal Name Type Description Output of the on-chip inverting oscillator amplifier XTAL2 O To use the internal oscillator, a crystal/resonator circuit is connected to this pin external oscillator ...
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... The TSC83251G2D products provide the internal program/code memory in a masked ROM memory while the TSC87251G2D products provide EPROM memory. For the TSC80251G2D products, there is no internal program/code memory and EA# must be tied to a low level. ...
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... This on-chip RAM is not accessible through the program/code memory space TSC83251G2D/TSC87251G2D, its upper 16 KB are also mapped in the upper part of the region 00: if the On-Chip Code Memory Map configuration bit is cleared (EMAP# bit in UCONFIG1 byte, see Figure ). However, if EA# is tied to a low level, the TSC80251G2D derivative is running as a ROMless product and the code is actually fetched in the corresponding external memory (i ...
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The Special Function Registers (SFRs) of the TSC80251G2D derivatives fall into the Special Function categories detailed in Table 1 to Table 9. Registers SFRs are placed in a reserved on-chip memory region S: which is not represented in the data ...
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Table 4. Serial I/O Port SFRs Table 5. SSLC SFRs Table 6. Event Waveform Control SFRs Mnemonic Name AT/TSC8x251G2D 14 Mnemonic Name SCON Serial Control SBUF Serial Data Buffer Slave Address SADEN Mask Mnemonic Name Synchronous Serial SSCON control Synchronous ...
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Table 7. System Management SFRs Mnemonic Name PCON POWM Table 8. Interrupt SFRs Mnemonic Name IE0 IE1 IPH0 Table 9. Keyboard Interface SFRs Mnemonic Name P1IE P1F 4135F–8051–11/06 Power Control CKRL Power Management WCON Interrupt Enable Control 0 IPL0 Interrupt ...
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Table 10. SFR Descriptions 0/8 1/9 CH F8h 0000 0000 (1) B F0h 0000 0000 CL E8h 0000 0000 (1) ACC E0h 0000 0000 CCON CMOD D8h 00X0 0000 00XX X000 (1) (1) PSW PSW1 D0h 0000 0000 0000 0000 ...
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The TSC80251G2D derivatives provide user design flexibility by configuring certain Configuration Bytes operating features at device reset. These features fall into the following categories: • • • • Two user configuration bytes UCONFIG0 (see Table 11) and UCONFIG1 (see Table ...
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Table 11. Configuration Byte 0 UCONFIG0 Bit Number Notes: AT/TSC8x251G2D WSA1# WSA0# XALE# Bit Mnemonic Description Reserved 7 - Set this bit when writing to UCONFIG0. 6 WSA1# Wait State A bits Select the ...
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... Number Bit Mnemonic Description On-Chip Code Memory Size bit CSIZE Clear to select on-chip code memory (TSC87251G1D TSC87251G2D product). 7 Set to select on-chip code memory (TSC87251G2D product). TSC80251G2D Reserved TSC83251G2D Set this bit when writing to UCONFIG1. Reserved 6 - Set this bit when writing to UCONFIG1. ...
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Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals Configuration Byte 1 Notes: AT/TSC8x251G2D 20 RD1 RD0 P1.7 P3.7/RD A17 A16 0 1 I/O pin A16 1 0 I/O pin I/O pin Read signal for ...
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Instruction Set This section contains tables that summarize the instruction set. For each instruction there is a short description, its length in bytes, and its execution time in states (one state Summary time is equal to two system clock cycles). ...
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Table 16. Notation for Immediate Addressing #data #data16 #0data16 #1data16 #short Table 17. Notation for Bit Addressing bit51 bit Table 18. Notation for Destination in Control Instructions rel addr11 addr16 addr24 AT/TSC8x251G2D 22 Immediate Address Description An 8-bit constant that ...
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Table 19. Notation for Register Operands Rmd Rms m, md, ms WRj WRjd WRjs at WRj at WRj +dis16 j, jd, js DRk DRkd DRks at DRk at DRk +dis16 k, kd, ks 4135F–8051–11/06 Register ...
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Table 20. Summary of Add and Subtract Instructions Size and Execution Time for Instruction Families AddADD <dest>, <src>dest opnd ← dest opnd + src opnd SubtractSUB <dest>, <src>dest opnd ← dest opnd - src opnd Add with CarryADDC <dest>, <src>(A) ...
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Table 21. Summary of Increment and Decrement Instructions IncrementINC <dest>dest opnd ← dest opnd + 1 IncrementINC <dest>, <src>dest opnd ← dest opnd + src opnd DecrementDEC <dest>dest opnd ← dest opnd - 1 DecrementDEC <dest>, <src>dest opnd ← dest ...
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Table 22. Summary of Compare Instructions CompareCMP <dest>, <src>dest opnd - src opnd Mnemonic CMP Notes: AT/TSC8x251G2D 26 <dest>, (2) <src> Comments Rmd, Rms Register with register WRjd, Word register with word register WRjs DRkd, Dword register with dword register ...
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ANL <dest>, <src>dest opnd ← dest opnd Λ src opnd Logical AND (1) Logical OR ORL <dest>, <src>dest opnd ← dest opnd ς src opnd (1) Logical Exclusive OR XRL <dest>, <src>dest opnd ← dest opnd ∀ src opnd ...
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Notes: 1. Logical instructions that affect a bit are in Table 27 shaded cell denotes an instruction in the C51 Architecture this instruction addresses an I/O Port (Px 0-3), add 1 to the number ...
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Table 24. Summary of Multiply, Divide and Decimal-adjust Instructions MultiplyMUL AB(B:A) ← (A)×(B) MUL <dest>, <src>extended dest opnd ← dest opnd × src opnd DivideDIV AB(A) ← Quotient ((A) ⁄ (B)) DivideDIV <dest>, <src>ext. dest opnd high ← Quotient (dest ...
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Table 25. Summary of Move Instructions (1/3) Move to High wordMOVH <dest>, <src>dest opnd Move with Sign extensionMOVS <dest>, <src>dest opnd ← src opnd with sign extend Move with Zero extensionMOVZ <dest>, <src>dest opnd ← src opnd with zero extend ...
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Table 26. Summary of Move Instructions (2/3) Move Mnemonic MOV Notes: 4135F–8051–11/06 (1) MOV <dest>, <src>dest opnd ← src opnd <dest>, (2) <src> Comments A, Rn Register to ACC Direct address (on-chip RAM or SFR) A, dir8 to ACC A, ...
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Move MOV <dest>, <src>dest opnd ← src opnd (1) Mnemonic <dest>, <src> Comments MOV Rmd, Rms Byte register to byte register MOV WRjd, WRjs Word register to word register MOV DRkd, DRks Dword register to dword register MOV Rm, ...
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WRj, at WRj MOV Indirect with 16-bit displacement (16M) to word register +dis24 at WRj +dis16, MOV Byte register to indirect with 16-bit displacement (64K WRj +dis16, MOV Word register to indirect with 16-bit displacement (64K) WRj at ...
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Table 27. Summary of Bit Instructions Clear BitCLR <dest>dest opnd ← 0 Set BitSETB <dest>dest opnd ← 1 Complement BitCPL <dest>dest opnd ← ∅ bit AND Carry with BitANL CY, <src>(CY) ← (CY) ∧ src opnd AND Carry with Complement ...
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Table 28. Summary of Exchange, Push and Pop Instructions Exchange bytesXCH A, <src>(A) ↔ src opnd Exchange DigitXCHD A, <src>(A) PushPUSH <src>(SP) ← (SP) +1; ((SP)) ← src opnd; PopPOP <dest>(SP) ← (SP) - size (dest opnd Mnemonic ...
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Table 29. Summary of Conditional Jump Instructions (1/2) Jump conditional on statusJcc rel(PC) ← (PC) + size (instr); Mnemonic JC JNC JE JNE JG JLE JSL JSLE JSG JSGE Notes: AT/TSC8x251G2D 36 IF [cc] THEN (PC) ← (PC) + rel ...
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Table 30. Summary of Conditional Jump Instructions (2/2) Jump if bitJB <src>, rel(PC) ← (PC) + size (instr); Jump if not bitJNB <src>, rel(PC) ← (PC) + size (instr); Jump if bit and clearJBC <dest>, rel(PC) ← (PC) + size ...
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Table 31. Summary of Unconditional Jump Instructions Absolute jumpAJMP <src>(PC) ← (PC) +2; (PC) Extended jumpEJMP <src>(PC) ← (PC) + size (instr); (PC) Long jumpLJMP <src>(PC) ← (PC) + size (instr); (PC) Short jumpSJMP rel(PC) ← (PC) +2; (PC) ← ...
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Table 32. Summary of Call and Return Instructions Absolute callACALL <src>(PC) ← (PC) +2; push (PC) Extended callECALL <src>(PC) ← (PC) + size (instr); push (PC) Long callLCALL <src>(PC) ← (PC) + size (instr); push (PC) Return from subroutineRETpop (PC) ...
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... All the internal non-volatile memory but the Signature Bytes of the TSC87251G2D prod- EPROM/OTPROM Devices ucts is made of EPROM cells. The Signature Bytes of the TSC87251G2D products are made of Mask ROM. The TSC87251G2D products are programmed and verified in the same manner as Atmel’s TSC87251G1A, using a SINGLE-PULSE algorithm, which programs less than 10 seconds for the 32 kilobytes on-chip code memory ...
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... The TSC87251G2D products implement 3 levels of security for User’s program as Lock Bit System described in Table 33. The TSC83251G2D products implement only the first level of security. Level 0 is the level of an erased part and does not enable any security features. Level 1 locks the programming of the User’s internal Code Memory, the Configuration Bytes and the Encryption Array. Level 2 locks the verifying of the User’ ...
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... Verify Algorithm, using the verify signature mode (see Table 37). Signature byte values are listed in Table 35. Table 35. Signature Bytes (Electronic ID) Vendor Architecture Memory Revision Programming Algorithm Figure 6 shows the hardware setup needed to program the TSC87251G2D EPROM/OTPROM areas: • • • • • • ...
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... PSEN# and the other control signals have to be released to complete a sequence of programming operations or a sequence of programming and verifying operations. VDD RST VPP EA#/VPP 100 ms pulses ALE/PROG# PSEN# TSC87251G2D Mode P0[7:0] A[7:0] P3[7:0] A[14:8] P1[7:0] Data P2[7:0] PSEN (1) ...
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Table 37. Verifying Modes ROM Area On-chip code memory Configuration Bytes Lock Bits Signature Bytes Notes: Figure 7. Setup for Verifying AT/TSC8x251G2D 44 Then device is driving the data on Port possible to alternate ...
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AC Characteristics - Commercial & Industrial AC Characteristics - External Bus Cycles Table 38. External Bus Cycles Timing Symbol Definitions Definition of Symbols Test conditions: capacitive load on all pins = 50 pF. Timings Table 39 and Table 40 list ...
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Table 39. Bus Cycles AC Timings; V Symbol Notes: AT/TSC8x251G2D 46 DD Parameter T 1/F OSC OSC T ALE Pulse Width LHLL T Address Valid to ALE Low AVLL T Address hold after ALE Low LLAX (1) T RD#/PSEN# Pulse ...
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Table 40. Bus Cycles AC Timings; V Notes: 4135F–8051–11/06 Symbol Parameter T 1/F OSC OSC T ALE Pulse Width LHLL T Address Valid to ALE Low AVLL T Address hold after ALE Low LLAX (1) T RD#/PSEN# Pulse Width RLRH ...
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Waveforms in Non-Page Mode Figure 8. External Bus Cycle: Code Fetch (Non-Page Mode) Note: Figure 9. External Bus Cycle: Data Read (Non-Page Mode) Note: AT/TSC8x251G2D 48 ALE TLHLL(1) PSEN P2/A16/A17 1. The value of this parameter depends on ...
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Figure 10. External Bus Cycle: Data Write (Non-Page Mode) Note: Figure 11. External Bus Cycle: Code Fetch (Page Mode) Waveforms in Page Mode Note: 4135F–8051–11/06 ALE TLHLL(1) WR# (1) T LHAX TAVLL(1) T LLAX A7:0 P0 (1) T AVWL1 (1) ...
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Figure 12. External Bus Cycle: Data Read (Page Mode) Note: Figure 13. External Bus Cycle: Data Write (Page Mode) Note: AC Characteristics - Real-Time Synchronous Wait State Table 41. Real-Time Synchronous Wait Timing Symbol Definitions Definition of Symbols AT/TSC8x251G2D 50 ...
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Table 42. Real-Time Synchronous Wait AC Timings; V Timings 85°C Waveforms Figure 14. Real-time Synchronous Wait State: Code Fetch/Data Read State 1 WCLK ALE RD#/PSEN# WAIT Figure 15. Real-time Synchronous Wait State: Data Write State 1 WCLK ALE ...
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AC Characteristics - Real-Time Asynchronous Wait State Table 43. Real-Time Asynchronous Wait Timing Symbol Definitions Definition of Symbols S Y Table 44. Real-Time Asynchronous Wait AC Timings; V Timings 85°C Note: Figure 16. Real-time Asynchronous Wait State Timings Waveforms AC ...
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Table 46. Serial Port AC Timing -Shift Register Mode; V Timings 85°C Note: Waveforms Figure 17. Serial Port Waveforms - Shift Register Mode T XLXL TXD T QVXH T XHQX RXD (Out XHDV RXD (In) Valid Valid ...
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AC Characteristics - SSLC: TWI Interface Table 47. TWI Interface AC Timing; V Timings Notes: Waveforms Figure 18. TWI Waveforms START or Repeated START condition SDA (INPUT/OUTPUT SCL (INPUT/OUTPUT) T ;STA HD AT/TSC8x251G2D 54 Symbol Parameter T ; ...
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AC Characteristics - SSLC: SPI Interface Table 48. SPI Interface Timing Symbol Definitions Definition of Symbols 4135F–8051–11/06 Signals C Clock I Data In O Data Out S SS# AT/TSC8x251G2D Conditions H High L Low V Valid X No Longer Valid ...
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Table 49. SPI Interface AC Timing; V Timings Notes: AT/TSC8x251G2D 56 ...
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Figure 19. SPI Master Waveforms (SSCPHA = 0) Waveforms (1) SS# (output) SCK (SSCPOL = 0) (output) SCK (SSCPOL = 1) (output) MISO (input) MOSI Port Data (output) Note: 1. SS# handled by software. Figure 20. SPI Master Waveforms (SSCPHA ...
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Figure 21. SPI Slave Waveforms (SSCPHA = 0) SS# (input) SCK (SSCPOL = 0) (input) SCK (SSCPOL = 1) (input) MISO (output) MOSI (input) Note: 1. Not Defined but generally the LSB of the character which has just been received. ...
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Table 51. EPROM Programming AC timings; V Timings Table 52. EPROM Verifying AC timings; V 40°C Waveforms Figure 23. EPROM Programming Waveforms P1 = A15 A7 D7 EA#/VPP ALE/PROG# P0 ...
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Figure 24. EPROM Verifying Waveforms P1 = A15 A7 D7 Characteristics - External Clock Drive and Logic Level References Table 53. External Clock Timing Symbol Definitions Definition of Symbols Table 54. External Clock AC ...
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Figure 26. AC Testing Input/Output Waveforms Note: Figure 27. Float Waveforms 4135F–8051–11/06 INPUTS V - 0 0 0.1 DD 0.45 V For timing purposes, a port pin is no longer floating when ...
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Absolute Maximum Rating and Operating Conditions Absolute Maximum Ratings Storage Temperature ......................................... -65 to +150°C Voltage on any other Pin to VSS ........................ -0 per I/O Pin ................................................................ Power Dissipation ........................................................... 1.5 W ...
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DC Characteristics High Speed Versions - Commercial, Industrial, and Automotive Table 55. DC Characteristics 4 Symbol Parameter Input Low Voltage V IL (except EA#, SCL, SDA) Input Low Voltage (5) V IL1 (SCL, ...
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Notes: 1. Under steady-state (non-transient) conditions, I Maximum IOL per port pin Maximum IOL per 8-bit port:Port Ports 1 Maximum Total IOL for all: Output Pins IOL exceeds the test ...
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Low Voltage Versions - Commercial & Industrial Table 56. DC Characteristics 2 Symbol Parameter Input Low Voltage V IL (except EA#, SCL, SDA) Input Low Voltage (5) V IL1 (SCL, SDA) Input Low ...
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Maximum Total IOL for all:Output Pins71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 and 2 ...
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Figure 31. I Figure 32. I 4135F–8051–11/06 Test Condition, Idle Mode DL RST TSC80251G2D (NC) XTAL2 Clock Signal XTAL1 VSS All other pins are unconnected Test Condition, Power-Down Mode PD RST TSC80251G2D (NC) XTAL2 XTAL1 VSS All other pins are ...
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Packages • List of Packages • • • • Figure 33. Plastic Dual In Line PDIL 40 - Mechanical Outline Table 57. PDIL Package Size AT/TSC8x251G2D 68 PDIL 40 CDIL 40 with window PLCC 44 CQPJ 44 with window VQFP ...
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Figure 34. Ceramic Dual In Line CDIL 40 with Window - Mechanical Outline Table 58. CDIL Package Size 4135F–8051–11/06 MM Min Max A - 5.71 b 0.36 0.58 b2 1.14 1.65 c 0.20 0. 53.47 E 13.06 15.37 ...
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Figure 35. Plastic Lead Chip Carrier PLCC 44 - Mechanical Outline Table 59. PLCC Package Size AT/TSC8x251G2D 70 MM Min Max A 4.20 4.57 A1 2.29 3.04 D 17.40 17.65 D1 16.44 16.66 D2 14.99 16.00 E 17.40 17.65 E1 ...
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Figure 36. Ceramic Quad Pack J CQPJ 44 with Window - Mechanical Outline Table 60. CQPJ Package Size 4135F–8051–11/06 MM Min 0. 17. 16.36 e 1.27 TYP f 0.43 J 0.86 ...
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Figure 37. Shrink Quad Flat Pack (Plastic) VQFP 44 (10x10) - Mechanical Outline Table 61. VQFP Package Size AT/TSC8x251G2D 72 MM Min Max A - 1.60 A1 0.64 REF A2 0.64 REF A3 1.35 1.45 D 11.90 12.10 D1 9.90 ...
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Ordering Information AT/TSC80251G2D ROMless TSC80251G2D-16CB TSC80251G2D-24CB TSC80251G2D-24CE TSC80251G2D-24IA TSC80251G2D-24IB AT80251G2D-SLSUM AT80251G2D-3CSUM AT80251G2D-RLTUM TSC80251G2D-L16CB TSC80251G2D-L16CE AT80251G2D-SLSUL AT80251G2D-RLTUL AT/TSC83251G2D 32 kilobytes MaskROM TSC251G2Dxxx-16CB TSC251G2Dxxx-24CB TSC251G2Dxxx-24CE TSC251G2Dxxx-24IA TSC251G2Dxxx-24IB AT251G2Dxxx-SLSUM AT251G2Dxxx-3CSUM AT251G2Dxxx-RLTUM AT251G2Dxxx-SLSTM 4135F–8051–11/06 Part Number ROM High Speed Versions 4.5 to 5.5 V, ...
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TSC251G2Dxxx-L16CB TSC251G2Dxxx-L16CE AT251G2Dxxx-SLSUL AT251G2Dxxx-RLTUL Note: 1. xxx: means ROM code, is Cxxx in case of encrypted code. AT/TSC8x251G2D 74 (1) Part Number ROM Description Low Voltage Versions 2.7 to 5.5 V 32K MaskROM 16 MHz, Commercial 0° to 70°C, PLCC ...
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... AT/TSC87251G2D OTPROM TSC87251G2D-16CB TSC87251G2D-24CB TSC87251G2D-24CED TSC87251G2D-24IA TSC87251G2D-24IB AT87251G2D-SLSUM AT87251G2D-3CSUM AT87251G2D-RLTUM TSC87251G2D-L16CB TSC87251G2D-L16CED AT87251G2D-SLSUL AT87251G2D-RLTUL Document Revision History 1. Added automotive qualification, and ordering information for ROM product version. Changes from 4135D to 4135E Changes from 1. Absolute Maximum Ratings added for automotive product version. ...
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... ROM code encryption Options (Please • Tape & Reel or Dry Pack consult Atmel sales) • Known good dice • Extended temperature range: -55°C to +125°C Product Markings AT/TSC8x251G2D 76 ROMless versions Mask ROM versions ATMEL ATMEL Part number Customer Part number Part Number YYWW ...
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... Atmel does not make any commitment to update the information contained herein. Unless specifically providedot- herwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as compo- nents in applications intended to support or sustain life. © ...