TS87C51RB2-VCA Atmel, TS87C51RB2-VCA Datasheet

IC MCU 8BIT 16K OTP 40MHZ 40-DIP

TS87C51RB2-VCA

Manufacturer Part Number
TS87C51RB2-VCA
Description
IC MCU 8BIT 16K OTP 40MHZ 40-DIP
Manufacturer
Atmel
Series
87Cr

Specifications of TS87C51RB2-VCA

Core Processor
8051
Core Size
8-Bit
Speed
40/30MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Active Errata List
Errata History
AT80C51RA2
TS80C51RB2
TS87C51RB2
Errata Descriptions
1. UART/Reception in Modes 1, 2 and 3/UART False Start Bits Detection
When a false start bit occurs on the UART, some UART internal signals are not reset.
Then when a real start bit occurs, the sampling is shifted.
Workaround
None.
2. During UART Reception, Clearing REN May Generate Unexpected IT
During UART reception, if the REN bit is clear between a start bit detection and the
end of reception, the UART will not discard the data (RI is set).
Workaround
Test REN at the beginning of Interrupt routine just after CLR RI, and run the Interrupt
routine code only if REN is set.
Lot Number
Lot Number
All
Lot Number
≤ 38584
> 38584
≤ 36425
> 36425
UART/Reception in Modes 1, 2 and 3/UART False Start Bits Detection
During UART Reception, Clearing REN May Generate Unexpected IT
JBC/Double IT When External IT Occurs During JBC Instruction
Timer2/Downcounter Mode/Double IT With Slow External Clock
Input Trigger Consumption/All C51 Type I/O Ports
MOVX/Port0/Read Mode
Errata List
T02,T03,T04,T05,T06
Errata List
T01, T02 ,T03, T04, T05, T06
T02 ,T03, T04, T05, T06
Errata List
T01, T02 ,T03, T04, T05, T06
T02 ,T03, T04, T05, T06
8051
Microcontrollers
TS87C51RB2
TS80C51RB2
AT80C51RA2
Errata Sheet
4154D–8051–03/08

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TS87C51RB2-VCA Summary of contents

Page 1

... During UART reception, if the REN bit is clear between a start bit detection and the end of reception, the UART will not discard the data (RI is set). Workaround Test REN at the beginning of Interrupt routine just after CLR RI, and run the Interrupt routine code only if REN is set. 8051 Microcontrollers TS87C51RB2 TS80C51RB2 AT80C51RA2 Errata Sheet 4154D–8051–03/08 ...

Page 2

JBC/Double IT When External IT Occurs During JBC Instruction On polling algorithm in ISR on IE1 or IE0, when the external IT appears during JBC instruction, the flag is not cleared. On the next JBC instruction another IT is ...

Page 3

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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