AT91RM9200-QI-002 SL383 Atmel, AT91RM9200-QI-002 SL383 Datasheet - Page 32

• Manufacturer Part Number: AT91RM9200-QI-002 SL383
• Description: IC ARM MCU 16BIT 128K 208PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002 SL383

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: AT91RM9200QI002SL

10.19 MultiMedia Card Interface
32
AT91RM9200
Table 10-6.
• Each channel is user-configurable and contains:
• Internal interrupt signal
• Two global registers that act on all three TC Channels
• The Timer Counter 0 to 5 are described with five generic clock inputs, TIMER_CLOCK1 to
• Compatibility with MultiMedia Card Specification Version 2.2
• Compatibility with SD Memory Card Specification Version 1.0
• Cards clock rate up to Master Clock divided by 2
• Embedded power management to slow down clock rate when not used
• Supports two slots
• Support for stream, block and multi-block data read and write
• Connection to a Peripheral DMA Controller (PDC) channel
TIMER_CLOCK5. In the AT91RM9200, these clock inputs are connected to the Master Clock
(MCK), to the Slow Clock (SLCK) and to divisions of the Master Clock. For details, see
Control” on page
Table 10-6
the AT91RM9200. Each Timer Counter 0 to 5 displays the same configuration.
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
– One slot for one MultiMedia Card bus (up to 30 cards) or one SD Memory Card
– Minimizes processor intervention for large buffer transfers
gives the correspondence between the Timer Counter clock inputs and clocks in
Timer Counter Clocks Assignment
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
TC Clock Input
488.
MCK/128
MCK/32
MCK/2
MCK/8
Clock
SLCK
1768MS–ATARM–09-Jul-09
”Clock