ATTINY85-20SI Atmel, ATTINY85-20SI Datasheet - Page 100

• Manufacturer Part Number: ATTINY85-20SI
• Description: IC AVR MCU 8K 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY85-20SI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

100
ATtiny25/45/85
Figure 13-3. Timer/Counter1 Block Diagram
Two status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag
Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1 and
GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask
Register - TIMSK.
The Timer/Counter1 contains two Output Compare Registers, OCR1A and OCR1C as the data
source to be compared with the Timer/Counter1 contents. In normal mode the Output Compare
functions are operational with OCR1A only. OCR1A determines action on the OC1A pin (PB1),
and it can generate Timer1 OC1A interrupt in normal mode and in PWM mode. OCR1C holds
the Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode
an overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while
in the PWM mode the overflow interrupt is generated when the Timer/Counter1 counts either
from $FF to $00 or from OCR1C to $00.
In PWM mode, OCR1A provides the data values against which the Timer Counter value is com-
pared. Upon compare match the PWM outputs (OC1A) is generated. In PWM mode, the Timer
Counter counts up to the value specified in the output compare register OCR1C and starts again
from $00. This feature allows limiting the counter “full” value to a specified value, lower than $FF.
Together with the many prescaler options, flexible PWM frequency selection is provided.
12-3 on page 91
20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM
frequencies can be obtained at the expense of resolution.
8-BIT DATABUS
COMPARE REGISTER
TIMER/COUNTER1
8-BIT COMPARATOR
REGISTER (TIMSK)
TIMER/COUNTER1
TIMER INT. MASK
T/C1 OUTPUT
T/C1 OVER-
FLOW IRQ
(OCR1A)
(TCNT1)
lists clock selection and OCR1C values to obtain PWM frequencies from
T/C1 COMPARE
MATCH A IRQ
T/C CLEAR
REGISTER (TIFR)
TIMER INT. FLAG
COMPARE REGISTER
8-BIT COMPARATOR
T/C1 OUTPUT
(OCR1C)
OC1A
(PB1)
REGISTER 1 (TCCR1)
T/C CONTROL
T/C1 CONTROL
LOGIC
GLOBAL T/C CONTROL
REGISTER 2 (GTCCR)
2586M–AVR–07/10
Table
CK
PCK