AT89C5131A-S3SIM Atmel, AT89C5131A-S3SIM Datasheet - Page 110
![IC 8051 MCU FLASH 32K USB 52PLCC](/photos/12/13/121324/453-52-plcc_sml.jpg)
AT89C5131A-S3SIM
Manufacturer Part Number
AT89C5131A-S3SIM
Description
IC 8051 MCU FLASH 32K USB 52PLCC
Manufacturer
Atmel
Series
AT89C513xr
Datasheet
1.AT89C5130A-PUTUM.pdf
(188 pages)
Specifications of AT89C5131A-S3SIM
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
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Table 20-5.
110
SSSTA
Status
Code
08h
10h
18h
20h
28h
30h
38h
Status of the Two-
wire Bus and Two-
wire Hardware
A START condition has
been transmitted
A repeated START
condition has been
transmitted
SLA+W has been
transmitted; ACK has
been received
SLA+W has been
transmitted; NOT ACK
has been received
Data byte has been
transmitted; ACK has
been received
Data byte has been
transmitted; NOT ACK
has been received
Arbitration lost in
SLA+W or data bytes
AT89C5130A/31A-M
Status in Master Transmitter Mode
To/From SSDAT
Write SLA+W
Write SLA+W
Write SLA+R
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
Application software response
SSSTA
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SSSTO
To SSCON
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
SSI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSAA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Next Action Taken by Two-wire Hardware
SLA+W will be transmitted.
SLA+W will be transmitted.
SLA+R will be transmitted.
Logic will switch to master receiver mode
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Two-wire bus will be released and not addressed
slave mode will be entered.
A START condition will be transmitted when the bus
becomes free.
4337K–USB–04/08
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