DSPIC30F3010T-20I/SO Microchip Technology, DSPIC30F3010T-20I/SO Datasheet - Page 44

• Manufacturer Part Number: DSPIC30F3010T-20I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010T-20I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F3010/3011
5.1
The user assignable Interrupt Priority (IP<2:0>) bits for
each individual interrupt source are located in the LS
3-bits of each nibble, within the IPCx register(s). Bit 3
of each nibble is not used and is read as a ‘0’. These
bits define the priority level assigned to a particular
interrupt by the user.
Since more than one interrupt request source may be
assigned to a specific user specified priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority”.
Natural Order Priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC devices and their associ-
ated vector numbers.
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PWM Fault
A Interrupt can be given a priority of 7. The INT0
(external interrupt 0) may be assigned to priority level
1, thus giving it a very low effective priority.
DS70141B-page 42
Note 1:
Note:
2: The natural order priority number is the
Interrupt Priority
The natural order priority scheme has 0 as the highest
priority and 53 as the lowest priority.
The user selectable priority levels start at
0, as the lowest priority, and level 7, as the
highest priority.
same as the INT number.
Preliminary
TABLE 5-1:
Highest Natural Order Priority
Lowest Natural Order Priority
* Available on dsPIC30F3011 only
Number
45-53
INT
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
11
0
1
2
3
4
5
6
7
8
9
Number
Vector
53-61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
8
9
INTERRUPT VECTOR TABLE
INT0 - External Interrupt 0
IC1 - Input Capture 1
OC1 - Output Compare 1
T1 - Timer 1
IC2 - Input Capture 2
OC2 - Output Compare 2
T2 - Timer 2
T3 - Timer 3
SPI #1
U1RX - UART1 Receiver
U1TX - UART1 Transmitter
ADC - ADC Convert Done
NVM - NVM Write Complete
SI2C - I
MI2C - I
Input Change Interrupt
INT1 - External Interrupt 1
IC7 - Input Capture 7
IC8 - Input Capture 8
OC3 - Output Compare 3*
OC4 - Output Compare 4*
T4 - Timer 4
T5 - Timer 5
INT2 - External Interrupt 2
U2RX - UART2 Receiver*
U2TX - UART2 Transmitter*
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWM - PWM Period Match
QEI - QEI Interrupt
Reserved
Reserved
FLTA - PWM Fault A
Reserved
Reserved
© 2005 Microchip Technology Inc.
2
2
Interrupt Source
C™ Slave Interrupt
C Master Interrupt