PIC16F716-I/ML Microchip Technology, PIC16F716-I/ML Datasheet - Page 298

IC PIC MCU FLASH 2KX14 28QFN

PIC16F716-I/ML

Manufacturer Part Number
PIC16F716-I/ML
Description
IC PIC MCU FLASH 2KX14 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F716-I/ML

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
PICmicro MID-RANGE MCU FAMILY
17.4.1.2
DS31017A-page 17-22
Slave Reception
When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the
SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.
When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An
overflow condition is defined as either the BF bit (SSPSTAT<0>) is set or the SSPOV bit
(SSPCON1<6>) is set.
An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in
software. The SSPSTAT register is used to determine the status of the received byte.
Note:
The SSPBUF will be loaded if the SSPOV bit is set and the BF flag bit is cleared. If
a read of the SSPBUF was performed, but the user did not clear the state of the
SSPOV bit before the next receive occurred. The ACK is not sent and the SSPBUF
is updated.
Preliminary
1997 Microchip Technology Inc.

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