DSPIC30F5015T-20I/PT Microchip Technology, DSPIC30F5015T-20I/PT Datasheet - Page 26

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DSPIC30F5015T-20I/PT

Manufacturer Part Number
DSPIC30F5015T-20I/PT
Description
IC DSPIC MCU/DSP 66K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F5015T-20I/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
For Use With
AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F5015T-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F
6.
FIGURE 2-7:
7.
FIGURE 2-8:
8.
DS70082G-page 24
1. PUSH DOEND
2. DO LABEL,#COUNT
2a.Second Word
3. 1st Instruction of Loop
1. MOV.b W0,[W1]
2. MOV.b [W1],PORTB
2a.Stall (NOP)
3. MOV.b W0,PORTB
Two-word instructions for DO. In these instruc-
tions, the fetch after the instruction contains an
address offset. This address offset is added to
the first instruction address to generate the last
loop instruction address. Therefore, these
instructions require 2 cycles, as shown in
Figure 2-7.
Instructions that are subjected to a stall due to a
data dependency between the X RAGU and X
WAGU. An additional cycle is inserted to resolve
the resource conflict, as shown in Figure 2-8.
Instruction stalls caused by data dependencies
are further discussed in Section 4.0.
Interrupt
Section 5.0 for details on interrupts.
recognition
INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE DO, DOW
INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION STALL
Fetch 1
T
Fetch 1
execution.
CY
T
0
CY
0
Execute 1
Fetch 2L
T
Execute 1
Fetch 2
Refer
CY
T
1
CY
1
to
Preliminary
NOP
Fetch 2H
T
NOP
Stall
CY
T
2
CY
2
Execute 2
Execute 2
Fetch 3
T
Fetch 3
CY
T
3
CY
3
Execute 3
T
Execute 3
CY
4
T
 2004 Microchip Technology Inc.
CY
4
T
CY
5

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