DSPIC33FJ64MC510-I/PT Microchip Technology, DSPIC33FJ64MC510-I/PT Datasheet - Page 202
![IC DSPIC MCU/DSP 64K 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ64MC510-I/PT
Manufacturer Part Number
DSPIC33FJ64MC510-I/PT
Description
IC DSPIC MCU/DSP 64K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.MA330013.pdf
(370 pages)
2.PIC24HJ12GP201-ISO.pdf
(84 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
4.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ64MC510-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
85
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64MC510-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC33FJ64MC510-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- MA330013 PDF datasheet
- PIC24HJ12GP201-ISO PDF datasheet #2
- DSPIC33FJ64MC506-IPT PDF datasheet #3
- DSPIC33FJ64MC506-IPT PDF datasheet #4
- Current page: 202 of 370
- Download datasheet (6Mb)
dsPIC33F
16.7.2
When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit timer will operate if QEISIDL (QEICON<13>) = 0.
This bit defaults to a logic ‘0’ upon executing POR. For
halting the timer module during the CPU Idle mode,
QEISIDL should be set to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally as if the CPU Idle mode had not been
entered.
16.8
The Quadrature Encoder Interface has the ability to
generate an interrupt on occurrence of the following
events:
• Interrupt on 16-bit up/down position counter
• Detection of qualified index pulse or if CNTERR
• Timer period match event (overflow/underflow)
• Gate accumulation event
The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS3 register.
Enabling an interrupt is accomplished via the respec-
tive enable bit, QEIIE. The QEIIE bit is located in the
IEC3 register.
DS70165E-page 200
rollover/underflow
bit is set
Quadrature Encoder Interface
Interrupts
TIMER OPERATION DURING CPU
IDLE MODE
Preliminary
16.9
The QEI module has four user-accessible registers.
The registers are accessible in either Byte or Word
mode. These registers are:
• Control/Status Register (QEICON) – This register
• Digital Filter Control Register (DFLTCON) – This
• Position Count Register (POSCNT) – This loca-
• Maximum Count Register (MAXCNT) – The MAX-
allows control of the QEI operation and status
flags indicating the module state.
register allows control of the digital input filter
operation.
tion allows reading and writing of the 16-bit posi-
tion counter.
CNT register holds a value that will be compared
to the POSCNT counter in some operations.
Note:
Control and Status Registers
The
accesses, however, reading the register in
byte mode may result in partially updated
values in subsequent reads. Either use
Word mode reads/writes or ensure that
the counter is not counting during byte
operations.
POSCNT
© 2007 Microchip Technology Inc.
register
allows
byte
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