AT87C51RD2-SLSUL Atmel, AT87C51RD2-SLSUL Datasheet - Page 22
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AT87C51RD2-SLSUL
Manufacturer Part Number
AT87C51RD2-SLSUL
Description
IC 8051 MCU 64K OTP 30MHZ 44PLCC
Manufacturer
Atmel
Series
87Cr
Datasheet
1.TS87C51RB2-VIA.pdf
(86 pages)
Specifications of AT87C51RD2-SLSUL
Core Processor
8051
Core Size
8-Bit
Speed
30/20MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
22
AT/TS8xC51Rx2
Reset Value = 0000 0000b
Bit addressable
Table 6-3.
Number
Bit
7
6
5
4
3
2
1
0
7
-
Mnemonic
CP/RL2#
EXEN2
RCLK
C/T2#
EXF2
TCLK
T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
TR2
TF2
Bit
6
-
Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is
enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode
(DCEN = 1)
Receive Clock bit
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if
timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock
out mode.
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2
overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
5
-
4
-
3
-
2
-
OSC
).
T2OE
1
4188F–8051–01/08
DCEN
0