ATTINY167-15MZ Atmel, ATTINY167-15MZ Datasheet - Page 195
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ATTINY167-15MZ
Manufacturer Part Number
ATTINY167-15MZ
Description
MCU AVR 16K FLASH 15MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY167-15MD.pdf
(283 pages)
Specifications of ATTINY167-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY167-15MZ
Manufacturer:
ATMEL
Quantity:
670
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17.5
7728G–AVR–06/10
Prescaling and Conversion Timing
Figure 17-3. ADC Prescaler
By default, the successive approximation circuitry requires an input clock frequency between
50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed,
the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA
register. The prescaler starts counting from the moment the ADC is switched on by setting the
ADEN bit in ADCSRA register. The prescaler keeps running for as long as the ADEN bit is set,
and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA register, the
conversion starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is
switched on (ADEN in ADCSRA register is set) takes 25 ADC clock cycles in order to initialize
the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal con-
version and 14.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conver-
sion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a
new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This
assures a fixed delay from the trigger event to the start of conversion. In this mode, the sam-
ple-and-hold takes place 2 ADC clock cycles after the rising edge on the trigger source signal.
Three additional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion
completes, while ADSC remains high. For a summary of conversion times, see
CLK
ADEN
Start
IO
ADPS0
ADPS1
ADPS2
Reset
7-bit ADC Prescaler
ATtiny87/ATtiny167
Table
17-1.
195
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