Z8F3201VN020EC00TR Zilog, Z8F3201VN020EC00TR Datasheet - Page 152

• Manufacturer Part Number: Z8F3201VN020EC00TR
• Description: IC ENCORE MCU FLASH 32K 44PLCC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F3201VN020EC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F3201VN020EC00T

PS017610-0404
Continuous Conversion
Caution:
1. Enable the desired analog inputs by configuring the general-purpose I/O pins for
2. Write to the ADC Control register to configure the ADC and begin the conversion.
3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
4. When the conversion is complete, the ADC control logic performs the following
5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
When configured for continuous conversion, the ADC continuously performs an analog-
to-digital conversion on the selected analog input. Each new data value over-writes the
previous value stored in the ADC Data registers. An interrupt is generated only at the end
of the first conversion after enabling.
The steps for setting up the ADC and initiating continuous conversion are as follows:
1. Enable the desired analog input by configuring the general-purpose I/O pins for
2. Write to the ADC Control register to configure the ADC for continuous conversion.
alternate function. This configuration disables the digital input and output drivers.
The bit fields in the ADC Control register can be written simultaneously:
–
–
–
–
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power-up
before beginning the 5129 cycle conversion.
operations:
–
–
–
powered-down.
alternate function. This disables the digital input and output driver.
The bit fields in the ADC Control register may be written simultaneously:
–
Write to ANAIN[3:0] to select one of the 12 analog input sources.
Clear CONT to 0 to select a single-shot conversion.
Write to VREF to enable or disable the internal voltage reference generator.
Set CEN to 1 to start the conversion.
10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}.
CEN resets to 0 to indicate the conversion is complete.
An interrupt request is sent to the Interrupt Controller.
In Continuous mode, users must be aware that ADC updates are limited by
the input signal bandwidth of the ADC and the latency of the ADC and its
digital filter. Step changes at the input are not seen at the next output from
the ADC. The response of the ADC (in all modes) is limited by the input
signal bandwidth and the latency.
Write to ANAIN[3:0] to select one of the 12 analog input sources.
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Analog-to-Digital Converter
Z8 Encore!
®
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