ZGP323LSH4804C00TR Zilog, ZGP323LSH4804C00TR Datasheet - Page 57

• Manufacturer Part Number: ZGP323LSH4804C00TR
• Description: IC Z8 GP MCU 4K OTP 48SSOP
• Manufacturer: Zilog
• Series: Z8® GP™r

Specifications of ZGP323LSH4804C00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: HLVD, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PS023709-0208
Note:
Note:
Table 14. Stop Mode Recovery Source
Any Port 2 bit defined as an output drives the corresponding input to the default state. For
example, if the NOR of P23-P20 is selected as the recovery source and P20 is configured
as an output, the remaining SMR pins (P23-P21) form the NOR equation. This condition
allows the remaining inputs to control the AND/OR function. See SMR2 register on
page 54 for other recover sources.
Stop Mode Recovery Delay Select (D5)
This bit, if Low, disables the T
configuration of this bit is 1. If the ‘fast’ wake up is selected, the Stop Mode Recovery
source must be kept active for at least 5 TpC.
It is recommended that this bit be set to 1 if using a crystal or resonator clock source. The
T
Stop Mode Recovery Edge Select (D6)
A 1 in this bit position indicates that a High level on any one of the recovery sources
wakes the device from STOP mode. A 0 indicates Low level recovery. The default is 0 on
POR.
Cold or Warm Start (D7)
This bit is read only. It is set to 1 when the device is recovered from STOP mode. The bit
is set to 0 when the device reset is other than Stop Mode Recovery.
SMR:432
D4
0
0
0
0
1
1
1
1
POR
delay allows the clock source to stabilize before executing instructions.
D3
0
0
1
1
0
0
1
1
D2
0
1
0
1
0
1
0
1
Operation
Description of Action
POR and/or external reset recovery
Reserved
P31 transition
P32 transition
P33 transition
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
POR
delay after Stop Mode Recovery. The default
Product Specification
Functional Description
ZGP323L
53