Z8F082ASH020SC Zilog, Z8F082ASH020SC Datasheet - Page 74

• Manufacturer Part Number: Z8F082ASH020SC
• Description: IC ENCORE XP MCU FLASH 8K 20SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F082ASH020SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 269-3684

Table 37. IRQ0 Enable High Bit Register (IRQ0ENH)
Table 38. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS022825-0908
IRQ1 Enable High and Low Bit Registers
Reserved
Reserved
R/W
R
7
0
7
0
Reserved—Must be 0.
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Reserved—Must be 0.
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
Table 39
registers
Interrupt Request 1 register.
T1ENH
T1ENL
(Table 40
describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit
R/W
R/W
6
0
6
0
and
T0ENH
T0ENL
R/W
R/W
Table
5
0
5
0
41) form a priority encoded enabling for interrupts in the
U0RENH
U0RENL
R/W
R/W
4
0
4
0
FC1H
FC2H
U0TENH
U0TENL
R/W
R/W
3
0
3
0
Z8 Encore! XP
Reserved Reserved
Reserved Reserved
R/W
R
2
0
2
0
Product Specification
R/W
R
1
0
1
0
®
Interrupt Controller
F082A Series
ADCENH
ADCENL
R/W
R/W
0
0
0
0
63