ZGP323HSP2004G Zilog, ZGP323HSP2004G Datasheet - Page 36

• Manufacturer Part Number: ZGP323HSP2004G
• Description: IC Z8 GP MCU 4K OTP 20DIP
• Manufacturer: Zilog
• Series: Z8® GP™r

Specifications of ZGP323HSP2004G

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: HLVD, POR, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4384; ZGP323HSP2004G

ZGP323H
Product Specification
31
Transmit_Submode/Glitch Filter
In TRANSMIT Mode, this field defines whether T8 and T16 are in the PING-PONG
mode or in independent normal operation mode. Setting this field to NORMAL OPERA-
TION Mode terminates the PING-PONG Mode operation. When set to 10, T16 is immedi-
ately forced to a 0; a setting of 11 forces T16 to output a 1.
In DEMODULATION Mode, this field defines the width of the glitch that must be filtered
out.
Initial_T8_Out/Rising_Edge
In TRANSMIT Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the out-
put of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is
set to 1 or 0, T8_OUT is set to the opposite state of this bit. This ensures that when the
clock is enabled, a transition occurs to the initial state set by CTR1, D1.
In DEMODULATION Mode, this bit is set to 1 when a rising edge is detected in the input
signal. In order to reset the mode, a 1 must be written to this location.
Initial_T16 Out/Falling _Edge
In TRANSMIT Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is
1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal
or PING-PONG Mode (CTR1, D3; D2). When the counter is not enabled and this bit is
set, T16_OUT is set to the opposite state of this bit. This ensures that when the clock is
enabled, a transition occurs to the initial state set by CTR1, D0.
In DEMODULATION Mode, this bit is set to 1 when a falling edge is detected in the input
signal. In order to reset it, a 1 must be written to this location.
Note:
Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output
from T8/16_OUT.
CTR2 Counter/Timer 16 Control Register—CTR2(D)02H
Table 9
lists and briefly describes the fields for this register.
PS023807-0707
Functional Description