MC68HC908GP32CFB Freescale Semiconductor, MC68HC908GP32CFB Datasheet - Page 314

• Manufacturer Part Number: MC68HC908GP32CFB
• Description: IC MCU 8MHZ 32K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Serial Peripheral Interface Module (SPI)
20.6.3 Transmission Format When CPHA = 1
Technical Data
312
CAPTURE STROBE
FOR REFERENCE
SPSCK; CPOL = 0
SPSCK; CPOL =1
SPSCK CYCLE #
FROM MASTER
SS; TO SLAVE
FROM SLAVE
MOSI
MISO
Figure 20-6. Transmission Format (CPHA = 1)
Figure 20-6
figure should not be used as a replacement for data sheet parametric
information. Two waveforms are shown for SPSCK: one for CPOL = 0
and another for CPOL = 1. The diagram may be interpreted as a master
or slave timing diagram since the serial clock (SPSCK), master in/slave
out (MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI.
begins driving its MOSI pin on the first SPSCK edge. Therefore, the
slave uses the first SPSCK edge as a start transmission signal. The SS
pin can remain low between transmissions. This format may be
preferable in systems having only one master and only one slave driving
the MISO data line.
(See 20.8.2 Mode Fault
Serial Peripheral Interface Module (SPI)
MSB
MSB
1
shows an SPI transmission in which CPHA is logic 1. The
BIT 6
BIT 6
2
BIT 5
BIT 5
3
BIT 4
BIT 4
4
Error.) When CPHA = 1, the master
BIT 3
BIT 3
MC68HC908GP32
5
BIT 2
BIT 2
6
BIT 1
BIT 1
7
•
MC68HC08GP32
LSB
8
LSB
MOTOROLA
—
Rev. 6