MC68HC711D3CFN2 Freescale Semiconductor, MC68HC711D3CFN2 Datasheet - Page 98

• Manufacturer Part Number: MC68HC711D3CFN2
• Description: IC MCU 2MHZ 4K OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Programmable Timer
8.5 Real-Time Interrupt
The real-time interrupt feature, used to generate hardware interrupts at a fixed periodic rate, is controlled
and configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL) register. The RTII
bit in the TMSK2 register enables the interrupt capability. The four different rates available are a product
of the MCU oscillator frequency and the value of bits RTR1 and RTR0. Refer to
real-time interrupt rates.
The clock source for the RTI function is a free-running clock that cannot be stopped or interrupted except
by reset. This clock causes the time between successive RTI timeouts to be a constant that is
independent of the software latencies associated with flag clearing and service. For this reason, an RTI
period starts from the previous timeout, not from when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is generated.
After reset, one entire real-time interrupt period elapses before the RTIF flag is set for the first time. Refer
to the TMSK2, TFLG2, and PACTL registers.
8.5.1 Timer Interrupt Mask 2 Register
The timer interrupt mask 2 register (TMSK2) contains the real-time interrupt enable bits.
TOI — Timer Overflow Interrupt Enable Bit
RTII — Real-Time Interrupt Enable Bit
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
PAII — Pulse Accumulator Input Edge Bit
Bits 3–2 — Unimplemented
98
Refer to
Refer to
Refer to
Always read 0.
0 = RTIF interrupts disabled
1 = Interrupt requested
8.4 Output Compare
8.7 Pulse
8.7 Pulse
Address:
Reset:
Read:
Write:
and RTR0
RTR1
0 0
0 1
1 0
1 1
Accumulator.
Accumulator.
$0024
Bit 7
TOI
Figure 8-16. Timer Interrupt Mask 2 Register (TMSK2)
0
Table 8-5. Periodic Real-Time Interrupt Rates
E = 1 MHz
10.923 ms
21.845 ms
RTII
2.731 ms
5.461 ms
(OC).
6
0
MC68HC711D3 Data Sheet, Rev. 2.1
PAOVI
5
0
E = 2 MHz
16.384 ms
32.768 ms
4.096 ms
8.192 ms
PAII
4
0
3
0
0
E = 3 MHz
16.384 ms
32.768 ms
65.536 ms
8.192 ms
2
0
0
PR1
1
0
E = X MHz
Table 8-5
(E/2
(E/2
(E/2
(E/2
Freescale Semiconductor
13
14
15
16
)
)
)
)
Bit 0
PR0
0
for the periodic