MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 140

• Manufacturer Part Number: MC68HC11E1CFN3
• Description: IC MCU 3MHZ 512 EEPROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Serial Peripheral Interface (SPI)
8.7.3 Serial Peripheral Data I/O Register
Data Sheet
140
WCOL — Write Collision Bit
Bit 5 — Unimplemented
MODF — Mode Fault Bit
Bits [3:0] — Unimplemented
The SPDR is used when transmitting or receiving data on the serial bus. Only a
write to this register initiates transmission or reception of a byte, and this only
occurs in the master device. At the completion of transferring a byte of data, the
SPIF status bit is set in both the master and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the
loss of the byte that caused the overrun, the first SPIF must be cleared by the time
a second transfer of data from the shift register to the read buffer is initiated.
SPI is double buffered in and single buffered out.
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set)
followed by an access of SPDR. Refer to
System
Always reads 0
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR.
Refer to
Always read 0
Address:
Reset:
Read:
Write:
0 = No write collision
1 = Write collision
0 = No mode fault
1 = Mode fault
Freescale Semiconductor, Inc.
For More Information On This Product,
Errors.
8.5.4 Slave Select
$102A
Figure 8-5. Serial Peripheral Data I/O Register (SPDR)
Bit 7
Bit 7
Serial Peripheral Interface (SPI)
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Bit 6
6
Bit 5
and
5
8.6 SPI System
Indeterminate after reset
Bit 4
4
8.5.4 Slave Select
Bit 3
3
Errors.
Bit 2
M68HC11E Family — Rev. 5
2
and
Bit 1
1
8.6 SPI
MOTOROLA
Bit 0
Bit 0