MC68HC11F1CPU4 Freescale Semiconductor, MC68HC11F1CPU4 Datasheet - Page 128

• Manufacturer Part Number: MC68HC11F1CPU4
• Description: IC MCU 512 EEPROM 4MHZ 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CPU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

10.1.5 A/D Converter Clocks
10.1.6 Conversion Sequence
10-4
E CLOCK
WRITE
ADCTL
indicates when valid data is present in the result registers. The result registers are writ-
ten during a portion of the system clock cycle when reads do not occur, so there is no
conflict.
The CSEL bit in the OPTION register selects whether the A/D converter uses the sys-
tem E clock or an internal RC oscillator for synchronization. When the A/D system is
operating with the MCU E clock, all switching and comparator functions are synchro-
nized to the MCU clocks. This allows the comparator results to be sampled at relatively
quiet clock times to minimize noise errors.
When E-clock frequency is below 750 kHz, charge leakage in the capacitor array can
cause errors, and the internal oscillator should be used. The RC clock is asynchronous
to the MCU internal E clock. Therefore, when the RC clock is used, additional errors
can occur because the comparator is sensitive to the additional system clock noise.
A/D converter operations are performed in sequences of four conversions each. A
conversion sequence can repeat continuously or stop after one iteration. The conver-
sion complete flag (CCF) is set after the fourth conversion in a sequence to show the
availability of data in the result registers. Figure 10-3 shows the timing of a typical se-
quence. Synchronization is referenced to the system E clock.
TO
0
AND UPDATE ADDR1
CONVERT FIRST
CHANNEL
SAMPLE ANALOG INPUT
12 E CYCLES
Freescale Semiconductor, Inc.
Figure 10-3 A/D Conversion Sequence
32
For More Information On This Product,
AND UPDATE ADDR2
CONVERT SECOND
ANALOG-TO-DIGITAL CONVERTER
CHANNEL
Go to: www.freescale.com
CYCLES
MSB
4
SUCCESSIVE APPROXIMATION SEQUENCE
64
BIT 6
CYC
2
AND UPDATE ADDR3
CONVERT THIRD
BIT 5
CYC
CHANNEL
2
BIT 4
CYC
2
BIT 3
CYC
2
96
BIT 2
CYC
2
AND UPDATE ADDR4
CONVERT FOURTH
BIT 1
CYC
CHANNEL
2
CYC
LSB
2
TECHNICAL DATA
CYC
END
MC68HC11F1
FLAG
2
SET
CCF
128
SEQUENCE
SCAN = 1
REPEAT
CYCLES
IF
E