MC68HC11F1CFN4 Freescale Semiconductor, MC68HC11F1CFN4 Datasheet - Page 47

• Manufacturer Part Number: MC68HC11F1CFN4
• Description: IC MCU 512 EEPROM 4MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

4.3.2 Initialization
4.3.2.1 CONFIG Register
CONFIG — System Configuration Register
EE[3:0] — EEPROM Mapping Control
TECHNICAL DATA
RESET:
Because bits in the following registers control the basic configuration of the MCU, an
accidental change of their values could cause serious system problems. The protec-
tion mechanism, overridden in special operating modes, requires a write to the protect-
ed bits only within the first 64 bus cycles after any reset, or only once after each reset.
Table 4-2 summarizes the write access limited registers.
CONFIG controls the presence and position of the EEPROM in the memory map.
CONFIG also enables the COP watchdog timer.
P indicates a previously programmed bit. P(L) indicates that the bit resets to the logic
level held in the latch prior to reset, but the function of COP is controlled by DISR bit
in TEST1 register.
The CONFIG register consists of an EEPROM byte and static latches that control the
start-up configuration of the MCU. The contents of the EEPROM byte are transferred
into static working latches during reset sequences. The operation of the MCU is con-
trolled directly by these latches and not by CONFIG itself. In normal modes, changes
to CONFIG do not affect operation of the MCU until after the next reset sequence.
When programming, the CONFIG register itself is accessed. When the CONFIG reg-
ister is read, the static latches are accessed.
These bits can be read at any time. The value read is the one latched into the register
from the EEPROM cells during the last reset sequence. A new value programmed into
this register cannot be read until after a subsequent reset sequence. Unused bits al-
ways read as ones.
In special test mode, the static latches can be written directly at any time. In all modes,
CONFIG bits can only be programmed using the EEPROM programming sequence,
and are neither readable nor active until latched via the next reset. Refer to 4.4.3 CON-
FIG Register Programming.
EE[3:0] select the upper four bits of the EEPROM base address. In single-chip and
bootstrap modes, EEPROM is forced to $FE00–$FFFF regardless of the value of
EE[3:0].
Bit 7
EE3
P
P
1
1
EE2
1
1
P
P
6
Freescale Semiconductor, Inc.
OPERATING MODES AND ON-CHIP MEMORY
For More Information On This Product,
EE1
P
P
5
1
1
Go to: www.freescale.com
EE0
P
P
4
1
1
—
3
1
1
1
1
NOCOP
P(L)
P(L)
P
P
2
—
1
1
1
1
1
EEON
Bit 0
P
1
1
0
Single Chip
Bootstrap
Expanded
Special Test
$103F
4-9