COP8CDR9IMT8 National Semiconductor, COP8CDR9IMT8 Datasheet - Page 65
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COP8CDR9IMT8
Manufacturer Part Number
COP8CDR9IMT8
Description
IC MCU CMOS 8BIT 48-TSSOP
Manufacturer
National Semiconductor
Series
COP8™ 8Cr
Datasheet
1.COP8CDR9HVA8NOPB.pdf
(84 pages)
Specifications of COP8CDR9IMT8
Core Processor
COP8
Core Size
8-Bit
Speed
20MHz
Connectivity
Microwire/Plus (SPI), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
*COP8CDR9IMT8
18.0 MICROWIRE/PLUS
18.1.2.1 Alternate SK Phase Operation and SK Idle
Polarity
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK idle polarity can be either high or low.
The polarity is selected by bit 5 of Port G data register. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK Phase
Alternate
Alternate
Normal
Normal
FIGURE 34. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low
FIGURE 33. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
G6 (SKSEL)
Config. Bit
TABLE 32. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase
0
1
0
1
Port G
(Continued)
G5 Data
Bit
0
0
1
1
SO Clocked Out On:
SK Falling Edge
SK Falling Edge
SK Rising Edge
SK Rising Edge
65
SK clock. In the alternate SK phase operation, data is shifted
in on the falling edge of the SK clock and shifted out on the
rising edge of the SK clock. Bit 6 of Port G configuration
register selects the SK edge.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Refer to Table 32 for
the appropriate setting of the SKSEL bit. The SKSEL is
mapped into the G6 configuration bit. The SKSEL flag will
power up in the reset condition, selecting the normal SK
signal provided the SK Idle Polarity remains LOW.
SI Sampled On:
SK Falling Edge
SK Falling Edge
SK Rising Edge
SK Rising Edge
10137436
10137437
www.national.com
SK Idle
Phase
High
High
Low
Low