MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 7
![IC MPU 32BIT W/CODE COMP 388PBGA](/photos/39/70/397084/bga-388_sml.jpg)
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1.2.3.4
1.2.3.5
MOTOROLA
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Automated queue modes initiated by:
— External edge trigger
— Software command
— Periodic/interval timer within QADC64E module, that can be assigned to both queue 1 and 2
— External gated trigger (queue 1 only)
64 result registers
— Output data is right- or left-justified, signed or unsigned.
Alternate reference input (ALTREF), with control in the conversion command word (CCW)
Three TouCAN modules (TouCAN A, TouCAN B, TouCAN C)
Each TouCAN provides the following features:
— 16 message buffers, programmable I/O modes
— Maskable interrupts
— Independent of the transmission medium (external transceiver is assumed)
— Open network architecture, multi-master concept
— High immunity to EMI
— Short latency time for high-priority messages
— Low-power sleep mode, with programmable wake-up on bus activity
— TouCAN C pins are shared with MIOS14 GPIO or QSMCM
One queued serial module with one queued SPI and two SCIs (QSMCM)
QSMCM matches full MPC555 QSMCM functionality
Queued SPI
— Provides full-duplex communication port for peripheral expansion or inter-processor
— Up to 32 preprogrammed transfers, reducing overhead
— Synchronous serial interface with baud rate of up to system clock / 4
— Four programmable peripheral-selects pins:
— Support up to 16 devices with external decoding
— Support up to eight devices with internal decoding
— Special wrap-around mode allows continuous sampling of a serial peripheral for efficient
SCI
— UART mode provides NRZ format and half- or full-duplex interface
— 16 register receive buffers and 16 register transmit buffers on one SCI
— Advanced error detection and optional parity generation and detection
— Word-length programmable as eight or nine bits
— Separate transmitter and receiver enable bits, and double buffering of data
— Wake-up functions allow the CPU to run uninterrupted until either a true idle line is detected,
communication
interfacing to serial analog-to-digital (A/D) converters
or a new address byte is received
Three CAN 2.0B Controller (TouCAN) Modules
Queued Serial Multi-Channel Module (QSMCM)
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC561/MPC563 Product Brief
Go to: www.freescale.com
Key Features
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