MC68332ACPV25 Freescale Semiconductor, MC68332ACPV25 Datasheet - Page 81

• Manufacturer Part Number: MC68332ACPV25
• Description: IC MCU 32-BIT 25MHZ A MASK
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACPV25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: Q1501580

PE — Parity Enable
M — Mode Select
WAKE — Wakeup by Address Mark
TIE — Transmit Interrupt Enable
TCIE — Transmit Complete Interrupt Enable
RIE — Receiver Interrupt Enable
ILIE — Idle-Line Interrupt Enable
TE — Transmitter Enable
RE — Receiver Enable
RWU — Receiver Wakeup
MC68332
MC68332TS/D
PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the re-
ceived parity bit is not correct, the SCI sets the PF error flag in SCSR.
When PE is set, the most significant bit (MSB) of the data field is used for the parity function, which re-
sults in either seven or eight bits of user data, depending on the condition of M bit. The following table
lists the available choices.
The transmitter retains control of the TXD pin until completion of any character transfer that was in
progress when TE is cleared.
Setting RWU enables the wakeup function, which allows the SCI to ignore received data until awakened
by either an idle line or address mark (as determined by WAKE). When in wakeup mode, the receiver
status flags are not set, and interrupts are inhibited. This bit is cleared automatically (returned to normal
mode) when the receiver is awakened.
0 = SCI parity disabled
1 = SCI parity enabled
0 = SCI frame: 1 start bit, 8 data bits, 1 stop bit (10 bits total)
1 = SCI frame: 1 start bit, 9 data bits, 1 stop bit (11 bits total)
0 = SCI receiver awakened by idle-line detection
1 = SCI receiver awakened by address mark (last bit set)
0 = SCI TDRE interrupts inhibited
1 = SCI TDRE interrupts enabled
0 = SCI TC interrupts inhibited
1 = SCI TC interrupts enabled
0 = SCI RDRF interrupt inhibited
1 = SCI RDRF interrupt enabled
0 = SCI IDLE interrupts inhibited
1 = SCI IDLE interrupts enabled
0 = SCI transmitter disabled (TXD pin may be used as I/O)
1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter)
0 = SCI receiver disabled (status bits inhibited)
1 = SCI receiver enabled
0 = Normal receiver operation (received data recognized)
1 = Wakeup mode enabled (received data ignored until awakened)
Freescale Semiconductor, Inc.
For More Information On This Product,
M
0
0
1
1
Go to: www.freescale.com
PE
0
1
0
1
8 Data Bits
7 Data Bits, 1 Parity Bit
9 Data Bits
8 Data Bits, 1 Parity Bit
Result
MOTOROLA
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