COP8SCR9KMT8 National Semiconductor, COP8SCR9KMT8 Datasheet - Page 28

IC MCU EEPROM 8BIT 32K 56-TSSOP

COP8SCR9KMT8

Manufacturer Part Number
COP8SCR9KMT8
Description
IC MCU EEPROM 8BIT 32K 56-TSSOP
Manufacturer
National Semiconductor
Series
COP8™ 8Sr
Datasheet

Specifications of COP8SCR9KMT8

Core Processor
COP8
Core Size
8-Bit
Speed
20MHz
Connectivity
Microwire/Plus (SPI), UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
*COP8SCR9KMT8
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11.0 In-System Programming
11.3.2 ISP Read Data Register
The Read Data Register (ISPRD) contains the value read
back from a read operation. This register can be accessed
from either flash program memory or Boot ROM. This regis-
ter is undefined on Reset.
11.3.3 ISP Write Data Register
The Write Data Register (ISPWR) contains the data to be
written into the specified address. This register is undeter-
mined on Reset. This register can be accessed from either
flash program memory or Boot ROM. The Write Data register
must be maintained for the entire duration of the operation.
(Continued)
Bit 7
Bit 7
Bit7
Bit7
R
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 6
Bit 6
Bit6
Bit6
TABLE 6. ISP Read Data Register
TABLE 7. ISP Write Data Register
R/W
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Bit 5
Bit 5
Bit5
Bit5
Bit 4
Bit 4
Bit4
Bit4
ISPWR
R/W
ISPRD
5
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
Bit 3
Bit 3
Bit3
Bit3
Bit 2
Bit 2
Bit2
Bit2
R/W
4
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
0
0
1
Register Bit
TABLE 8. PGMTIM Register Format
Bit 1
Bit 1
Bit1
Bit1
R/W
Bit 0
Bit 0
Bit0
Bit0
3
0
0
0
0
0
0
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
0
1
1
PGMTIM
28
R/W
11.3.4 ISP Write Timing Register
The Write Timing Register (PGMTIM) is used to control the
width of the timing pulses for write and erase operations. The
value to be written into this register is dependent on the
frequency of CKI and is shown in Table 8. This register must
be written before any write or erase operation can take
place. It only needs to be loaded once, for each value of CKI
frequency. This register can be loaded from either flash
program memory or Boot ROM and must be maintained for
the entire duration of the operation. The MICROWIRE/PLUS
ISP routine that is resident in the boot ROM requires that this
Register be defined prior to any access to the Flash memory.
Refer to 11.7 MICROWIRE/PLUS ISP for more information
on available ISP commands. On Reset, the PGMTIM regis-
ter is loaded with the value that corresponds to 10 MHz
frequency for CKI.
2
0
0
0
1
1
1
0
0
1
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
R/W
1
0
1
1
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
1
0
1
1
1
1
R/W
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
CKI Frequency Range
200 kHz–266.67 kHz
500 kHz–666.67 kHz
800 kHz–1.067 MHz
1.125 MHz–1.5 MHz
2.625 MHz–3.5 MHz
112.5 kHz–150 kHz
3.5 MHz–4.67 MHz
62.5 kHz–83.3 kHz
50 kHz–66.67 kHz
100 kHz–133 kHz
150 kHz–200 kHz
225 kHz–300 kHz
300 kHz–400 kHz
375 kHz–500 kHz
600 kHz–800 kHz
1 MHz–1.33 MHz
2 MHz–2.67 MHz
7.5 MHz–10 MHz
25 kHz–33.3 kHz
37.5 kHz–50 kHz
75 kHz–100 kHz
1.5 MHz–2 MHz
4.5 MHz–6 MHz
6 MHz–8 MHz

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