C8051F310 Silicon Laboratories Inc, C8051F310 Datasheet - Page 221
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C8051F310
Manufacturer Part Number
C8051F310
Description
IC 8051 MCU 16K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Specifications of C8051F310
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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19. Revision Specific Behavior
This chapter contains behavioral differences between C8051F310/1 “REV A” and “REV B” or later devices.
These differences do not affect the functionality or performance of most systems and are described below.
19.1. Revision Identification
The Lot ID Code on the top side of the device package can be used for decoding device revision informa-
tion. On C8051F310 devices, the revision letter is the second-to-last letter of the Lot ID Code. On
C8051F311 devices, the revision letter is the last letter of the Lot ID Code. Figure 19.1 shows how to find
the Lot ID Code on the top side of the device package.
19.2. Reset Behavior
The reset behavior of C8051F310/1 “REV A” devices is different than “REV B” and later devices. The dif-
ferences affect the state of the RST pin during a V
19.2.1. Weak Pullups on GPIO Pins
On “REV A” devices, GPIO pins are tri-stated with weak pullups disabled during the assertion phase of
any reset. The pullups are enabled immediately following reset de-assertion.
On “REV B” and later devices, GPIO pins are tri-stated with weak pullups enabled during and after the
assertion phase of any reset.
19.2.2. V
On “REV A” devices, a V
On “REV B” and later devices, a V
out condition.
C8051F310
T2ABGFAC
0227 EP
C8051F310 Package Marking
DD
Monitor and the RST Pin
^ indicates REV A
DD
Monitor reset does not affect the state of the RST pin.
Figure 19.1. Reading Package Marking
DD
Monitor reset will pull the RST pin low for the duration of the brown-
Rev. 1.7
DD
Monitor reset and GPIO pins during any device reset.
C8051F310/1/2/3/4/5/6/7
CYG
F311
ABGFA
C8051F311 Package Marking
^ indicates REV A
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