MC9328MX1VH20 Freescale Semiconductor, MC9328MX1VH20 Datasheet - Page 34

• Manufacturer Part Number: MC9328MX1VH20
• Description: IC MCU I.MX 200MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX1r

Specifications of MC9328MX1VH20

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 110
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-MAPBGA
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Functional Description and Application Information
4.4.2.4
34
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Number
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
10
11
12
7
8
9
OE
DATABUS
Wait asserted to RW negated
Data hold timing after RW negated
Data ready after CS5 is asserted
EB negated after CS5 is negated
Wait becomes low after CS5 asserted
Wait pulse width
Address
WAIT Write Cycle DMA Enabled
(logic high)
WAIT
CS5
RW
1
EB
2
Characteristic
programmable
min 0ns
programmable
9
min 0ns
Figure 9. WAIT Write Cycle DMA Enabled
12
MC9328MX1 Technical Data, Rev. 7
6
3
13
1.5T+0.74
Minimum
2.5T-1.18
1T+2.15
1T
–
0
7
3.0 ± 0.3 V
8
4
11
Maximum
1.5T+2.35
2T+7.34
1019T
1020T
Freescale Semiconductor
–
T
10
5
Unit
ns
ns
ns
ns
ns
ns