C8051F130 Silicon Laboratories Inc, C8051F130 Datasheet
C8051F130
Manufacturer Part Number
C8051F130
Description
IC 8051 MCU 128K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F130
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1147
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F130
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F130-GQ
Manufacturer:
SiliconL
Quantity:
2 490
Company:
Part Number:
C8051F130-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F130-GQ
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
C8051F130-GQR
Manufacturer:
TI
Quantity:
679
Company:
Part Number:
C8051F130-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Analog Peripherals
10-Bit ADC
-
-
-
-
-
-
Two Comparators
Internal Voltage Reference
V
On-Chip JTAG Debug & Boundary Scan
-
-
-
-
-
General Purpose
MONEN
DD
XTAL1
XTAL2
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
DGND
DGND
DGND
AGND
AGND
VREF
±1 LSB INL; no missing codes
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
CP0+
CP1+
CP0-
CP1-
VDD
VDD
VDD
TMS
TDO
AV+
AV+
TCK
RST
TDI
Monitor/Brown-out Detector
CP0
Analog Power
Digital Power
M
A
U
X
External Oscillator
Calibrated Internal
Monitor
VDD
Oscillator
CP1
JTAG
Logic
Circuit
VREF
SENSOR
TEMP
Circuitry
Prog
Gain
PLL
Boundary Scan
WDT
Debug HW
100 MIPS, 128 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU
100ksps
(10-Bit)
System
Clock
ADC
Reset
Copyright © 2004 by Silicon Laboratories
C
o
8
0
5
1
e
r
External Data
Memory Bus
64x4 byte
128kbyte
256 byte
SFR Bus
FLASH
8kbyte
XRAM
cache
RAM
High-Speed 8051 µC Core
-
-
-
Memory
-
-
-
Digital Peripherals
-
-
-
-
-
-
Clock Sources
-
-
-
Supply Voltage: 3.0 to 3.6 V
-
-
100-Pin TQFP
Temperature Range: –40 to +85 °C
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 100 MIPS throughput with 100 MHz system clock
16 x 16 multiply/accumulate engine (2-cycle)
8448 bytes data RAM
128 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
are reserved)
External parallel data memory interface
64 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
Programmable 16-bit counter/timer array with six capture/compare
modules
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using timer 3 or PCA
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
On-chip programmable PLL: up to 100 MHz
External oscillator: Crystal, RC, C, or Clock
Typical operating current: 50 mA at 100 MHz
Typical stop mode current: 0.4 µA
Timers 0,
Crossbar
Timer 3/
Port I/O
SPI Bus
Latches
UART0
UART1
SMBus
P0, P1,
Config.
Config.
P2, P3
1, 2, 4
PCA
RTC
Address Bus
Bus Control
Data Bus
C
T
A
D
L
d
d
a
a
r
t
C
R
O
B
A
R
S
S
P4 Latch
P5 Latch
P6 Latch
P7 Latch
C8051F130
P0
Drv
P1
Drv
P2
Drv
P3
Drv
DRV
DRV
DRV
DRV
P4
P5
P6
P7
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
P3.0
P3.7
8.9.2004
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A15
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7
Related parts for C8051F130
C8051F130 Summary of contents
Page 1
... PCA RAM Timers 8kbyte XRAM Timer 3/ 1 RTC P0, P1, P2, P3 External Data Latches Memory Bus C Crossbar Config FLASH 128kbyte e 64x4 byte cache Copyright © 2004 by Silicon Laboratories C8051F130 P0.0 P0 Drv P0 P1.0/AIN2 Drv P1.7/AIN2 P2 Drv P2 P3.0 P3 Drv P3.7 P4 Latch Bus Control P4 P4 ...
Page 2
... A2 0.95 1.00 1.05 b 0.17 0.22 0. 16. 14. 0. 16. 14.00 - Copyright © 2004 by Silicon Laboratories C8051F130 TYP MAX UNITS 3 — mA 0.6 — — µA 10 — µA 0.4 — µA — 100 MHz 24.5 25.0 MHz — 100 MHz 10 bits — ±1 LSB — ...