C8051F045 Silicon Laboratories Inc, C8051F045 Datasheet - Page 162
C8051F045
Manufacturer Part Number
C8051F045
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1157
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C8051F040/1/2/3/4/5/6/7
162
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
-
Reserved.
EP1: UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low level.
1: UART1 interrupt set to high level.
PCAN0: CAN Interrupt Priority Control.
This bit sets the priority of the CAN Interrupt.
0: CAN Interrupt set to low priority level.
1: CAN Interrupt set to high priority level.
PADC2: ADC2 End Of Conversion Interrupt Priority Control (C8051F040/1/2/3 only).
This bit sets the priority of the ADC2 End of Conversion interrupt.
0: ADC2 End of Conversion interrupt set to low level.
1: ADC2 End of Conversion interrupt set to low level.
PWADC2: ADC2 Window Comparator Interrupt Priority Control (C8051F040/1/2/3 only).
0: ADC2 Window interrupt set to low level.
1: ADC2 Window interrupt set to high level.
PT4: Timer 4 Interrupt Priority Control.
This bit sets the priority of the Timer 4 interrupt.
0: Timer 4 interrupt set to low level.
1: Timer 4 interrupt set to low level.
PADC0: ADC End of Conversion Interrupt Priority Control.
This bit sets the priority of the ADC0 End of Conversion Interrupt.
0: ADC0 End of Conversion interrupt set to low priority level.
1: ADC0 End of Conversion interrupt set to high priority level.
PT3: Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupts.
0: Timer 3 interrupt set to low priority level.
1: Timer 3 interrupt set to high priority level.
EP1
SFR Definition 12.16. EIP2: Extended Interrupt Priority 2
R/W
Bit6
PX7
R/W
Bit5
PADC2
R/W
Bit4
PWADC2
Rev. 1.5
R/W
Bit3
PT4
R/W
Bit2
PADC0
R/W
Bit1
SFR Address:
SFR Page:
PT3
R/W
Bit0
0xF7
All Pages
00000000
Reset Value
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