R5F21102FP Renesas Electronics America, R5F21102FP Datasheet - Page 9

IC R8C MCU FLASH 8K 32LQFP

R5F21102FP

Manufacturer Part Number
R5F21102FP
Description
IC R8C MCU FLASH 8K 32LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/10r
Datasheet

Specifications of R5F21102FP

Core Processor
R8C
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
LED, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0E521134CPE00 - EMULATOR COMPACT R8C/13
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21102FP#U0
Manufacturer:
Renesas Electronics America
Quantity:
1 787
Part Number:
R5F21102FP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/10 Group
Rev.1.60
REJ03B0035-0160
2. Central Processing Unit (CPU)
Figure 2.1 CPU Register
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. Two sets of register banks are provided.
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The
R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data
registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be
used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0.
Jan 27, 2006
b 3 1
NOTES:
1. A regist er bank comprises t hese regist ers. Two set s of regist er banks are provided
page 7 of 25
R 2
R 3
b15
IPL
b 1 9
b 1 9
The 4-high order bits of INTB are INTBH and
the 16-low bits of INTB are INTBL.
I N T B H
b 1 5
b 1 5
b15
b15
R 0 H ( h i g h - o r d e r o f R 0 )
R1H (high-order of R1)
b8
b7
U
P C
I
I N T B L
USP
ISP
FLG
b 8 b7
SB
R2
R 3
A 0
A 1
F B
O
R 0 L ( h i g h - o r d e r o f R 0 )
R1L (high-order of R1)
B
S
Z
D
C
b 0
b 0
b 0
b0
b0
b0
Data registers
Address registers
Frame base registers
Interrupt table register
Program counter
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
2. Central Processing Unit (CPU)
(1)
(1)
(1)

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