HD6417604SF28 Renesas Electronics America, HD6417604SF28 Datasheet
HD6417604SF28
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HD6417604SF28 Summary of contents
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ADE-602-085C Rev. 4.0 9/19/01 Hitachi, Ltd. SH7604 Hardware Manual ...
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...
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The SH7604 implements high-performance operations by using a CPU which employs the Reduced Instruction Set Computer (RISC) system. The SH7604 is a new-generation RISC microcomputer which realizes low power consumption, an essential feature of microcomputer devices, as well as integrating ...
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List of Items Revised or Added for This Version Section Page Item Description (see Manual for details) ...
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Bus Width of the CS0 Area................................................................................................ 62 3.4 Switching between Master Mode and Slave Mode............................................................ 63 Section 4 Exception Handling 4.1 Overview............................................................................................................................ 65 4.1.1 Types of Exception Handling and Priority Order ................................................. 65 4.1.2 Exception Handling Operations............................................................................ 66 4.1.3 ...
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IRL Interrupts........................................................................................................ 83 5.2.4 On-chip Peripheral Module Interrupts.................................................................. 85 5.2.5 Interrupt Exception Vectors and Priority Order.................................................... 86 5.3 Description of Registers..................................................................................................... 88 5.3.1 Interrupt Priority Level Setting Register A (IPRA).............................................. 88 5.3.2 Interrupt Priority Level Setting Register B (IPRB) ...
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Section 7 Bus State Controller (BSC) 7.1 Overview............................................................................................................................ 129 7.1.1 Features ................................................................................................................. 129 7.1.2 Block Diagram...................................................................................................... 130 7.1.3 Pin Configuration.................................................................................................. 132 7.1.4 Register Configuration.......................................................................................... 134 7.1.5 Address Map ......................................................................................................... 134 7.2 Description of Registers..................................................................................................... 136 7.2.1 Bus Control Register 1 ...
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Burst Access.......................................................................................................... 194 7.7.5 Refreshing ............................................................................................................. 195 7.7.6 Power-On Sequence.............................................................................................. 197 7.8 Burst ROM Interface.......................................................................................................... 197 7.9 Waits between Access Cycles............................................................................................ 200 7.10 Bus Arbitration................................................................................................................... 201 7.10.1 Master Mode ......................................................................................................... 203 7.10.2 Slave Mode ........................................................................................................... 205 7.10.3 Partial-Share Master ...
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Register Descriptions ......................................................................................................... 235 9.2.1 DMA Source Address Registers 0 and 1 (SAR0 and SAR1) ............................... 235 9.2.2 DMA Destination Address Registers 0 and 1 (DAR0 and DAR1) ...................... 236 9.2.3 DMA Transfer Count Registers 0 and 1 (TCR0 ...
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Section 11 16-Bit Free-Running Timer 11.1 Overview............................................................................................................................ 295 11.1.1 Features ................................................................................................................. 295 11.1.2 Block Diagram...................................................................................................... 296 11.1.3 Pin Configuration.................................................................................................. 297 11.1.4 Register Configuration.......................................................................................... 297 11.2 Register Descriptions ......................................................................................................... 298 11.2.1 Free-Running Counter (FRC) ............................................................................... 298 11.2.2 Output Compare Registers A ...
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Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 329 12.4 Usage Notes ....................................................................................................................... 330 12.4.1 Contention between WTCNT Write and Increment ............................................. 330 12.4.2 Changing CKS2 to CKS0 Bit Values ................................................................... 330 12.4.3 Switching between Watchdog Timer and Interval ...
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Standby Mode Cancellation by NMI.................................................................... 391 14.4.4 Clock Pause Function ........................................................................................... 391 14.4.5 Notes on Standby Mode........................................................................................ 393 14.5 Module Standby Function.................................................................................................. 393 14.5.1 Transition to Module Standby Function ............................................................... 393 14.5.2 Clearing the Module Standby Function................................................................ 393 Section ...
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Section 1 Overview and Pin Functions 1.1 SH7604 Features The SH7604 is a new-generation single-chip RISC microprocessor that integrates a Hitachi- original CPU, a multiplier, cache memory, and peripheral functions required for system configuration. The CPU features a RISC-type instruction ...
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On-chip multiplier: multiply operations (32 bits accumulate operations (32 bits 32 bits + 64 bits Five-stage pipeline Operating Modes: Clock mode: selected from the combination of an on-chip oscillator module, a frequency multiplier, clock output, PLL synchronization, and 90 phase ...
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Clock Pulse Generator (CPG)/Phase Locked Loop (PLL): On-chip clock pulse generator Crystal clock source or external clock source can be selected Clock multiplication ( 1, 2, 4), PLL synchronization phase shift can be selected Supports clock pause function ...
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Direct Memory Access Controller (DMAC) (2 Channels): Division Unit (DIVU): ...
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... Product Lineup: Product Code Package HD6417604SF28 QFP2020-144 HD6417604SFI28 QFP2020-144 HD6417604SVF20 QFP2020-144 HD6417604SBP28 CSP-1313-176 HD6417604SVBP20 CSP-1313-176 Operating Temperature Frequency - MHz - MHz - MHz - MHz - MHz Voltage 3 3 ...
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WDTOVF BREQ BGR BACK BRLS WAIT RD CASLL WE0 CASLH WE1 CASHL WE2 CASHH WE3 CAS OE RAS CS3 CS2 CS1 ...
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Pin No. FP-144 TBP-176 Pin Name I/O Pin Description ...
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Pin No. FP-144 TBP-176 Pin Name I/O Pin Description ...
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Pin No. FP-144 TBP-176 Pin Name CS0 I/O Pin Description ...
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Pin No. FP-144 TBP-176 Pin Name CS1 CS2 CS3 BS WR RAS CE CAS OE CASHH CASHL CASLH CASLL RD WAIT BACK BRLS BREQ BGR WDTOVF I/O Pin Description WE3 WE2 WE1 WE0 ...
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Pin No. FP-144 TBP-176 Pin Name CKPACK CKPREQ I/O Pin Description ...
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Pin No. FP-144 TBP-176 Pin Name RES IVECF IRL3 IRL2 IRL1 IRL0 I/O Pin Description ...
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Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 General Registers The 16 general registers (R0–R15) are shown in figure 2.1. General registers are used for data ...
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Control Registers The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR) (figure 2.2). The status register indicates processing states. The global base register functions as a base address ...
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System Registers System registers consist of four 32-bit registers: high and low multiply-and-accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC) (figure 2.3). The multiply-and-accumulate registers store the results of multiply and accumulate operations. ...
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Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits) (figure 2.4). When the memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when loaded ...
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Immediate Data Format Byte (8-bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, ...
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Delayed Branch Instructions: Unconditional branch instructions are delayed. Executing the instruction that follows the branch instruction, before branching reduces pipeline disruption during branching (table 2.3). Table 2.3 Delayed Branch Instructions SH7604 Series CPU Description Executes ADD before BRA TRGET branching ...
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Table 2.5 Immediate Data Accessing Classification SH7604 CPU 8-bit immediate MOV #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 ................. .DATA.W H'1234 32-bit immediate MOV.L @(disp,PC),R0 ................. .DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data. Absolute Address: When data is accessed by ...
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Addressing Modes Table 2.8 shows addressing modes and effective address calculation. Table 2.8 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Addresses Calculation Register direct Rn The effective address is register Rn. (The operand is the contents ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Addresses Calculation Register @(disp:4, The effective address is Rn plus a 4-bit indirect with Rn) displacement (disp). The value of disp is zero- displacement extended, and remains ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Addresses Calculation PC relative @(disp:8, The effective address is the PC value plus an 8-bit with PC) displacement (disp). The value of disp is zero- displacement extended, ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Addresses Calculation PC relative Rn The effective address is the register PC value (cont) plus Rn. Immediate #imm:8 The 8-bit immediate data (imm) for the TST, AND, ...
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Table 2.9 Instruction Formats Instruction Format 0 format 15 0 xxxx xxxx xxxx xxxx n format 15 0 xxxx nnnn xxxx xxxx m format 15 0 xxxx mmmm xxxx xxxx 26 Destination Source Operand Operand — — — nnnn: Register ...
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Table 2.9 Instruction Formats (cont) Instruction Format nm format 15 0 xxxx nnnn mmmm xxxx md format 15 0 xxxx xxxx mmmm dddd nd4 format 15 0 xxxx xxxx nnnn dddd nmd format 15 0 xxxx nnnn dddd mmmm Destination ...
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Table 2.9 Instruction Formats (cont) Instruction Format d format 15 0 xxxx xxxx dddd dddd d12 format 15 0 xxxx dddd dddd dddd nd8 format 15 0 xxxx nnnn dddd dddd i format 15 0 xxxx xxxx ...
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Instruction Set 2.4.1 Instruction Set by Classification Table 2.10 Instruction Set by Classification Operation Classification Types Code Data transfer 5 MOV MOVA MOVT SWAP XTRCT Arithmetic 21 ADD operations ADDC ADDV CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU DT ...
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Table 2.10 Instruction Set by Classification (cont) Operation Classification Types Code Logic 6 AND operations NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch BRA BRAF BSR BSRF ...
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Table 2.10 Instruction Set by Classification (cont) Operation Classification Types Code System 11 CLRT control CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total:62 Function T bit clear MAC register clear Load to control register Load to system ...
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Table 2.11 Instruction Code Format Item Format Instruction OP.Sz mnemonic SRC,DEST Instruction MSB LSB code Operation , summary (xx) M/Q/T & <<n, >>n Execution — states T bit — Notes: 1. Depending on the operand size, displacement ...
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Table 2.12 Data Transfer Instructions Instruction Instruction Code MOV #imm,Rn 1110nnnniiiiiiii MOV.W @(disp,PC),Rn 1001nnnndddddddd MOV.L @(disp,PC),Rn 1101nnnndddddddd MOV Rm,Rn 0110nnnnmmmm0011 MOV.B Rm,@Rn 0010nnnnmmmm0000 MOV.W Rm,@Rn 0010nnnnmmmm0001 MOV.L Rm,@Rn 0010nnnnmmmm0010 MOV.B @Rm,Rn 0110nnnnmmmm0000 MOV.W @Rm,Rn 0110nnnnmmmm0001 MOV.L @Rm,Rn 0110nnnnmmmm0010 MOV.B Rm,@–Rn ...
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Table 2.12 Data Transfer Instructions (cont) Instruction Instruction Code MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 MOV.B R0,@(disp,GBR) 11000000dddddddd MOV.W R0,@(disp,GBR) 11000001dddddddd MOV.L R0,@(disp,GBR) 11000010dddddddd MOV.B @(disp,GBR),R0 11000100dddddddd MOV.W @(disp,GBR),R0 11000101dddddddd MOV.L @(disp,GBR),R0 11000110dddddddd MOVA @(disp,PC),R0 11000111dddddddd MOVT ...
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Table 2.13 Arithmetic Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn 0011nnnnmmmm0111 CMP/PZ Rn 0100nnnn00010001 ...
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Table 2.13 Arithmetic Instructions (cont) Instruction Instruction Code DMULU.L Rm,Rn 0011nnnnmmmm0101 DT Rn 0100nnnn00010000 EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 MAC @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn ...
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Table 2.13 Arithmetic Instructions (cont) Instruction Instruction Code SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV Rm,Rn 0011nnnnmmmm1011 Note: The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with preceding ...
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Table 2.15 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 SHLL2 Rn 0100nnnn00001000 SHLR2 Rn 0100nnnn00001001 SHLL8 Rn 0100nnnn00011000 ...
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Table 2.16 Branch Instructions Instruction Instruction Code BF label 10001011dddddddd BF/S label 10001111dddddddd BT label 10001001dddddddd BT/S label 10001101dddddddd BRA label 1010dddddddddddd BRAF Rm 0000mmmm00100011 BSR label 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP @Rm 0100mmmm00101011 JSR @Rm 0100mmmm00001011 RTS 0000000000001011 Note: ...
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Table 2.17 System Control Instructions Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 LDC.L @Rm+,VBR 0100mmmm00100111 LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 LDS.L ...
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Table 2.17 System Control Instructions (cont) Instruction Instruction Code STS MACH,Rn 0000nnnn00001010 STS MACL,Rn 0000nnnn00011010 STS PR,Rn 0000nnnn00101010 STS.L MACH,@–Rn 0100nnnn00000010 STS.L MACL,@–Rn 0100nnnn00010010 STS.L PR,@–Rn 0100nnnn00100010 TRAPA #imm 11000011iiiiiiii Note: The number of execution states before the chip enters ...
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Operation Code Map Table 2.18 Operation Code Map Instruction Code Fx: 0000 MSB LSB MD: 00 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn Fx 0010 STC SR,Rn 0000 Rm Fx 0011 BSRF Rm 0000 Rn Rm ...
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Table 2.18 Operation Code Map (cont) Instruction Code Fx: 0000 MSB LSB MD: 00 0100 Rn Fx 0001 SHLR Rn 0100 Rn Fx 0010 STS.L MACH, @–Rn 0100 Rn Fx 0011 STC.L SR,@–Rn 0100 Rn Fx 0100 ROTL Rn 0100 ...
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Table 2.18 Operation Code Map (cont) Instruction Code Fx: 0000 MSB LSB MD: 00 1000 10MD imm/disp CMP/EQ #imm:8,R0 1000 10MD imm/disp 1001 Rn disp MOV.W @(disp:8,PC),Rn 1010 disp BRA label:12 1011 disp BSR label:12 1100 00MD imm/disp MOV.B R0, ...
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From any state when RES = 0 and NMI = 1 Power-on reset state RES = 1, NMI = 1 Interrupt or DMA address error Bus request cleared Bus-released state Bus request generated Bus request Bus request cleared generated SLEEP ...
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Reset State: The CPU resets in the reset state. This occurs when the RES pin level goes low. When the NMI pin is high, the result is a power-on reset; when it is low, a manual reset will occur. Exception ...
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To return from standby mode, use a reset or an external NMI interrupt. For resets, the CPU returns to the ordinary program execution state through the exception handling state when placed in a reset state after the oscillator stabilization time ...
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Table 2.19 Power-Down State Mode Conditions Clock Sleep Execute Active SLEEP instruction with SBY bit cleared SBYCR Standby Execute Halted SLEEP instruction with SBY bit set SBYCR Module MSTP4– Active standby MSTP0 bits of ...
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Section 3 Oscillator Circuits and Operating Modes 3.1 Overview Operation of the on-chip clock pulse generator, CS0 area bus width specification, and switching between master and slave modes are controlled by the operating mode pins. A crystal resonator or external ...
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Pin Configuration: Table 3.1 lists the functions relating to the pins relating to the oscillator circuit. Table 3.1 Pin Functions Pin Name I/O Function CKIO I/O External clock input pin or internal clock output pin XTAL O Connects to the ...
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Clock Operating Mode Settings Table 3.2 lists the functions and operation of clock modes Note that TBP-176 package products can only be used in clock modes Table 3.2 Operating Modes Clock Mode Function/Operation ...
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Table 3.3 Clock Mode Pin Settings and States CKPREQ/ Clock Mode MD2 MD1 MD0 CKM ...
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CKPREQ/CKM Output or high CKIO impedance EXTAL XTAL Rd Figure 3.2 Example of Crystal Resonator Connection Table 3.4 Damping Resistance (Reference Values) Frequency (MHz 500 Crystal Resonator: Figure 3.3 shows a crystal resonator equivalent circuit. Use ...
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Inputting an External Clock Input the external clock from the EXTAL pin or the CKIO pin, depending on the clock mode. Clock Input from the EXTAL Pin: This can be used in clock modes 0,1, 2, and 3. CKPREQ/CKM ...
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CAP2 XTAL f Oscillator EXTAL Figure 3.6 Relationship between PLL Circuit 2 and the Frequency Modification Register PLL circuit 2 includes the PLL circuit (which quadruples frequency f of clocks generated by the oscillator) and frequency dividers, which divide the ...
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Bits 2–7 are reserved. They always read 0, and the write value should always be 0. Modifying Frequencies: In the following modifications, the device is running in clock modes and the operating frequency is left unchanged, doubled, ...
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Frequency Modification Register Setting Program (Sample) ; DEFINE CONSTANTS CLR .EQU WAIT_TIME .EQU PURGE .EQU ; MAP_ROM .EQU MAP-IO .EQU ; DIRECT_RW .EQU MDC_FLCR .EQU MDC_CCR .EQU WTCSR .EQU ; ; Program initialization MOV.L MOV.L MOV.L ; Cache_CCR save, disable, ...
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MOV.L R3,@(4,R1) MOV.L R4,@(8,R1) MOV.L R5,@(12,R1) ; Increment pointer ADD #H'10,R0 ADD #H'10,R1 ; Loop CMP/GT R11,R0 BF PRG_TRNS ; Branch to the data array forced access space MOV.L #DIRECT_RW,R0 JMP @R0 NOP *2 .CONST ; CLOCK2_START MOV.L MOV.L MOV.L ...
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NOP NOP NOP NOP NOP NOP NOP ; Branch to the next program JMP NOP *2 .CONST CLOCK2_END ; ; Next program NEXT_PROG ; Cache_CCR load MOV.L MOV Notes: *1 This example shows Hitachi cross-assembler coding. With ...
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Operating Modes and Frequency Ranges Table 3.7 shows the operating modes and the associated frequency ranges for input clocks. Table 3.7 Operating Modes and Frequency Ranges PLL Circuit Mode PLL1 PLL2 Pin 0 Active Active EXTAL 1 (including when ...
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No crossing of signal lines Figure 3.8 Design Considerations when Using a Crystal Resonator When Using PLL Oscillation Circuits: Place oscillation settling capacitors C1 and C2 and resistors R1 and R2 near the CAP1 and CAP2 pins, and keep the ...
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SH7604 Note: CPB/CB: 0.1 F (laminated ceramic) Rp: 300 resistance (recommended value) Figure 3.9 Design Considerations when Using PLL Oscillation Circuits 3.3 Bus Width of the CS0 Area Pins MD3 and MD4 are used to specify the bus width of ...
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Switching between Master Mode and Slave Mode The SH7604 has two master modes and a slave mode for bus rights that can be selected with the MD5 pin. The master modes consist of a total master mode and a ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Types of Exception Handling and Priority Order Exception handling is initiated by four sources: resets, address errors, interrupts, and instructions (table 4.1). When several exception handling sources occur at once, they are processed ...
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Exception Handling Operations Exception handling sources are detected, and exception handling started, according to the timing shown in table 4.2. Table 4.2 Timing of Exception Source Detection and Start of Exception Handling Exception Source Reset Power-on reset Manual reset ...
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Exception Vector Table Before exception handling begins, the exception vector table must be written in memory. The exception vector table stores the start addresses of exception service routines. (The reset exception table holds the initial values of PC and ...
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Table 4.3 Exception Processing Vector Table (cont) Exception Source *1 Interrupt IRL1 *1 IRL2 *1 IRL3 *1 IRL4 *1 IRL5 *1 IRL6 *1 IRL7 *1 IRL8 *1 IRL9 *1 IRL10 *1 IRL11 *1 IRL12 *1 IRL13 *1 IRL14 *1 IRL15 ...
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Table 4.4 Calculating Exception Vector Table Addresses Exception Source Vector Table Address Calculation Power-on reset (Vector table address) = (vector table address offset) Manual reset Other exception handling (Vector table address) = VBR + (vector table address offset) Note: VBR: ...
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Power-On Reset When the NMI pin is high and the RES pin is driven low, the device performs a power-on reset. For a reliable reset, the RES pin should be kept low for at least the duration of the ...
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Address Errors 4.3.1 Sources of Address Errors Address errors occur when instructions are fetched or data read or written, as shown in table 4.6. Table 4.6 Bus Cycles and Address Errors Bus Cycle Bus Type Master Bus Cycle Description ...
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Address Error Exception Handling When an address error occurs, address error exception handling begins after the end of the bus cycle in which the error occurred and completion of the executing instruction. The CPU operates as follows: 1. The ...
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Interrupt Priority Levels The interrupt priority order is predetermined. When multiple interrupts occur simultaneously, the interrupt controller (INTC) determines their relative priorities and begins exception handling accordingly. The priority order of interrupts is expressed as priority levels 0–16, with ...
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Exceptions Triggered by Instructions 4.5.1 Instruction-Triggered Exception Types Exception handling can be triggered by a trap instruction, general illegal instruction or illegal slot instruction, as shown in table 4.9. Table 4.9 Types of Exceptions Triggered by Instructions Type Source ...
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The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code or the ...
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Immediately after an Interrupt-Disabled Instruction When an instruction immediately following an interrupt-disabled instruction is decoded, interrupts are not accepted. Address errors are accepted. 4.7 Stack Status after Exception Handling The status of the stack after exception handling ends is ...
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Address Errors Caused by Stacking of Address Error Exception Handling If the stack pointer value is not a multiple of four, an address error will occur during stacking of the exception handling (interrupts, etc.). Address error exception handling will ...
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Section 5 Interrupt Controller (INTC) 5.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which allow the user to ...
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NMI IR3–IR0 A3–A0 Input/ output IVECF control D7–D0 (Interrupt request) UBC (Interrupt request) DMAC (Interrupt request) DIVU (Interrupt request) FRT (Interrupt request) SCI (Interrupt request) WDT (Interrupt request) REF ICR Module bus VCRWDT VCRWDT, VCRA–VCRD UBC: User break controller DMAC: ...
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Pin Configuration Table 5.1 shows the INTC pin configuration. Table 5.1 Pin Configuration Name Nonmaskable interrupt input pin Level request interrupt input pins Interrupt acceptance level output pins External vector fetch pin External vector number input pins 5.1.4 Register ...
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Table 5.2 Register Configuration Name Interrupt priority level setting register A Interrupt priority level setting register B Vector number setting register A Vector number setting register B Vector number setting register C Vector number setting register D Vector number setting ...
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IRL Interrupts IRL interrupts are requested by input from pins IRL3–IRL0. Fifteen interrupts, IRL15–IRL1, can be input externally via pins IRL3–IRL0. The priority levels of interrupts IRL15–IRL0 are 15–1, respectively, and their vector numbers are 71–64. Set the vector ...
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Interrupt requests Vector number Figure 5.2 Example of Connections for External Vector Mode Interrupts Interrupt requests Figure 5.3 Example of Connections for Auto-Vector Mode Interrupts Figure 5.4 shows the interrupt fetch cycle for the external vector mode. During this cycle, ...
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CKIO CS0–CS3 BS A3–A0 IVECF RD/WR RD D7–D0 WAIT Figure 5.4 External Vector Mode Interrupt Vector Fetch Cycle 5.2.4 On-chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following 6 on-chip peripheral modules: Division unit (DIVU) ...
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Interrupt Exception Vectors and Priority Order Table 5.4 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses ...
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Table 5.4 Interrupt Exception Vectors and Priority Order Interrupt Priority Order (Initial Interrupt Source Value) NMI 16 User break 15 IRL15 15 IRL14 14 IRL13 13 IRL12 12 IRL11 11 IRL10 10 IRL9 9 IRL8 8 IRL7 7 IRL6 6 ...
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Table 5.4 Interrupt Exception Vectors and Priority Order (cont) Interrupt Priority Order (Initial Interrupt Source Value) DMAC0 Transfer end 0–15 (0) DMAC1 Transfer end WDT ITI 0–15 (0) *3 REF CMI SCI ERI 0–15 (0) RXI TXI TEI FRT ICI ...
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Bit Bit name: DIVU DIVU IP3 IP2 Initial value: 0 R/W: R/W R/W Bit: 7 Bit name: WDT WDT IP3 IP2 Initial value: 0 R/W: R/W R/W Bits 15 to 12—Division Unit (DIVU) Interrupt Priority Level (DIVUIP3–DIVUIP0): These ...
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Bit Bit name: SCIIP3 SCIIP2 Initial value: 0 R/W: R/W R/W Bit: 7 Bit name: — — Initial value: 0 R/W: R Bits 15 to 12—Serial Communication Interface (SCI) Interrupt Priority Level (SCIIP3– SCIIP0): These bits set the ...
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Vector Number Setting Register WDT (VCRWDT) Vector number setting register WDT (VCRWDT 16-bit read/write register that sets the WDT interval interrupt and BSC compare match interrupt vector numbers (0–127). VCRWDT is initialized to H'0000 by a reset. ...
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Bit Bit name: — SERV6 Initial value: 0 R/W: R R/W Bit: 7 Bit name: — SRXV6 Initial value: 0 R/W: R R/W Bits 15, 7—Reserved: These bits always read 0. The write value should always be 0. ...
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Bits 15, 7—Reserved: These bits always read 0. The write value should always be 0. Bits 14 to 8—Serial Communication Interface (SCI) Transmit-Data-Empty Interrupt Vector Number (STXV6–STXV0): These bits set the vector number for the serial communication interface (SCI) transmit-data-empty ...
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Vector Number Setting Register D (VCRD) Vector number setting register D (VCRD 16-bit read/write register that sets the FRT overflow interrupt vector number (0–127). VCRD is initialized to H'0000 by a reset not initialized in ...
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As table 5.6 shows, two on-chip peripheral module interrupts are assigned to each register. Set the vector numbers by setting the corresponding 7-bit groups (bits and bits with values in the range of H'00 ...
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Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. Bit 15: NMIL Description 0 NMI input level ...
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Interrupt Operation 5.4.1 Interrupt Sequence The sequence of interrupt operations (figure 5.5) is explained below: 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt among the interrupt ...
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Program execution state Interrupt No generated? Yes No NMI? Yes User break? Yes Yes Save SR to stack Save PC to stack Copy accepted interrupt level to I3–I0 Read vector number* Read exception vector table Branch to exception service routine ...
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Stack after Interrupt Exception Handling Figure 5.6 shows the stack after interrupt exception handling. Address 4n – – Note: PC: Start address of next instruction after the executing instruction (return destination instruction) Figure 5.6 Stack ...
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Interrupt Response Time Table 5.8 shows the interrupt response time, which is the time from the occurrence of an interrupt request until interrupt exception handling starts and fetching of the first instruction of the interrupt service routine begins. Figure ...
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IRL3–IRL0 Instruction (instructions replaced during interrupt exception handling) Overrun fetch Interrupt service routine start instruction When the interrupt response time is 13 cycles F: Instruction fetch (instruction fetched from memory where program is ...
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IRL0 IRL1 Noise canceler IRL2 IRL3 Pin level cleared when interrupt is accepted Figure 5.8 Interrupt Response Block Diagram 1011 for 1 clock IRL3–IRL0 due to pin level noise 1111 1111 Noise canceler output 1111 Interrupt request to CPU Interrupt ...
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Usage Notes 1. Do not execute module standby for modules that have the module-stop function when the possibility remains that an interrupt request may be output shown in figure 5.10, the point at which the NMI request ...
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Interrupt clear instruction ex. mov r0,@r1 Synchronization instruction ex. mov @r1,r0 RTE instruction Delay slot instruction Instruction at destination of return from interrupt IRL3–IRL0 Figure 5.11 Pipeline Operation in Return with RTE Interrupt clear instruction ex. mov r0,@r1 Synchronization instruction ...
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On-Chip Interrupt Sources: Pipeline operation must be taken into account to ensure that the same interrupt does not occur again when the interrupt source is from an on-chip peripheral module. At least 2 cycles are required for the CPU to ...
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Interrupt clear instruction ex. mov r0,@r1 Synchronization instruction ex. mov @r1,r0 LDC instruction Interrupt-disable instruction Ordinary instruction On-chip peripheral interrupt Figure 5.14 Pipeline Operation when Interrupts are Enabled by Changing the SR 106 Next interrupt can be accepted Writing complete ...
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Section 6 User Break Controller 6.1 Overview The user break controller (UBC) provides functions that simplify program debugging. Break conditions are set in the UBC and a user break interrupt is generated according to the conditions of the bus cycle ...
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Block Diagram BARAH/L: Break address register AH/L BAMRAH/L: Break address mask register AH/L BBRA: Break bus cycle register A BARBH/L: Break address register BH/L BAMRBH/L: Break address mask register BH/L BDRBH/L: Break data register BH/L BDMRBH/L: Break data mask ...
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Register Configuration Table 6.1 Register Configuration Name Break address register AH Break address register AL Break address mask register AH Break address mask register AL Break bus cycle register A Break address register BH Break address register BL Break ...
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Register Descriptions 6.2.1 Break Address Register A (BARA) BARAH: Bit Bit name: BAA31 BAA30 Initial value: 0 R/W: R/W R/W Bit: 7 Bit name: BAA23 BAA22 Initial value: 0 R/W: R/W R/W BARAL: Bit Bit ...
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Break Address Mask Register A (BAMRA) BAMRAH: Bit Bit name: BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 Initial value: 0 R/W: R/W R/W Bit: 7 Bit name: BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 Initial ...
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Bits 31–0: BAMAn Description 0 Channel A break address BAAn is included in the break conditions 1 Channel A break address BAAn is masked and therefore not included in the break conditions 6.2.3 Break Bus ...
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Bit 7: CPA1 Bit 6: CPA0 Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): These bits select whether to break channel A on instruction fetch and/or data access cycles. Bit 5: IDA1 ...
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Break Address Register B (BARB) The channel B break address register has the same bit configuration as BARA. 6.2.5 Break Address Mask Register B (BAMRB) The channel B break address mask register has the same bit configuration as BAMRA. ...
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BDRBH Bits 15 to 0—Break Data (BDB31 to BDB16): These bits store the upper half (bits 31–16) of the data that is the break condition for break channel B. BDRBL Bits 15 to 0—Break Data B ...
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BDMRBH Bits 15 to 0—Break Data Mask (BDMB31 to BDMB16): These bits specify whether bits B 31–16 (BDB31 to BDB16) of the channel B break data set in BDRBH are masked. BDMRBL Bits 15 to 0—Break ...
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The BRCR register: 1. Determines whether to use channels A and B as two independent channels or as sequential conditions. 2. Selects SH7000 series compatible mode or SH7604 mode. 3. Selects whether to break before or after instruction execution during ...
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Bit 12—UBC Mode (UMD): Selects SH7000 series-compatible mode or SH7604 mode. Bit 12: UMD Description 0 Compatible mode for SH7000 Series UBCs 1 SH7604 mode Bit 11—Reserved: This bit always reads 0. The write value should always be 0. Bit ...
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Bit 5—Reserved: This bit always reads 0. The write value should always be 0. Bit 4—Sequence Condition Select (SEQ): Selects whether to handle the channel A and B conditions independently or sequentially. Bit 4: SEQ Description 0 Channel A and ...
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Operation 6.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break interrupt exception handling is described below: 1. The break addresses are set in the break address registers (BARA, BARB), the masked ...
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An instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a ...
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B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31–16 of BDRB and BDMRB are ignored. 6.3.4 Break on External Bus ...
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Example of Use Break on a CPU Instruction Fetch Bus Cycle: A. Register settings: BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054 BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054 BDRB = H'00000000, BDMRB = H'00000000 BRCR ...
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C. Register settings: BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054 BDRB = H'00000000, BDMRB = H'00000000 BRCR = H'1000 Conditions set (channel A/channel B independent mode): Channel A: Address ...
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Break on CPU Data Access Cycle: Register settings: BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064 BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A BDRB = H'0000A512, BDMRB = H'00000000 BRCR = H'1008 Conditions set (channel A/channel B ...
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Usage Notes 1. UBC registers can only be read or written to by the CPU. 2. When set for a sequential break, conditions match when a match of channel B conditions occurs some time after the bus cycle in ...
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SH7000 Series Compatible Mode 1. In SH7000 Series compatible mode: In SH7000 Series compatible mode, functions are as follows: The registers shown in the table 6.2 are valid; all others are not. External bus breaks are not possible in ...
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128 ...
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Section 7 Bus State Controller (BSC) 7.1 Overview The bus state controller (BSC) manages the address spaces and outputs control signals so that optimum memory accesses can be made in the four spaces. This enables memories like DRAM, synchronous DRAM ...
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Master and slave modes (bus arbitration) Total master and partial-share master modes. In total master mode, all resources are shared with other CPUs. Bus permission is shared when an external bus release request is received. In partial-share master mode, only ...
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WAIT CS3–CS0 BS RD CAS RAS RD/WR WE3–WE0 CKE IVECF CMI interrupt request Interrupt controller WCR: Wait control register BCR: Bus control register MCR: Individual memory control register Figure 7.1 BSC Block Diagram interface Wait WCR control unit BCR1 Area ...
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Pin Configuration Table 7.1 lists the bus state controller pin configuration. Table 7.1 Pin Configuration With Bus Signal I/O Released Description A26–A0 I/O I Address bus. 27 bits are available to specify a total 128 Mbytes of memory space. ...
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Table 7.1 Pin Configuration (cont) With Bus Signal I/O Released Description CASLH, When DRAM is used, connected to CAS pin for the third byte O Hi-Z DQMLU, (D15–D8). When synchronous DRAM is used, connected to DQM WE1 pin for the ...
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Register Configuration The BSC has seven registers. These registers are used to control wait states, bus width, interfaces with memories like DRAM, synchronous DRAM, pseudo-SRAM, and burst ROM, and DRAM, synchronous DRAM, and pseudo-SRAM refreshing. The register configurations are ...
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Table 7.3 Address Map Address Space H'00000000 to H'01FFFFFF CS0 space, cache area H'02000000 to H'03FFFFFF CS1 space, cache area H'04000000 to H'05FFFFFF CS2 space, cache area H'06000000 to H'07FFFFFF CS3 space, cache area H'08000000 to H'1FFFFFFF Reserved H'20000000 to ...
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Description of Registers 7.2.1 Bus Control Register 1 (BCR1) Bit Bit name: MASTER — Initial value: — R/W: R Bit: 7 Bit name: A1LW1 A1LW0 Initial value: 1 R/W: R/W R/W Initialize ENDIAN, BSTROM, PSHR and DRAM2–DRAM0 ...
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Bit 11—Area 0 Burst ROM Enable (BSTROM) Bit 11: BSTROM Description 0 Area 0 is accessed normally 1 Area 0 is accessed as burst ROM Bit 10—Partial Space Share Specification (PSHR): When bus arbitration is in master mode and the ...
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Bit 5: A0LW1 Bit 4: A0LW0 Bits 2 to 0—Enable for DRAM and Other Memory (DRAM2–DRAM0) DRAM2 DRAM1 DRAM0 Description Areas 2 and 3 are ordinary spaces 1 Area 2 is ...
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Bits 15 to 8—Reserved: These bits always read 0. The write value should always be 0. Bits 7 and 6—Bus Size Specification for Area 3 (A3SZ1–A3SZ0). Effective only when ordinary space is set. Bit 7: A3SZ1 Bit 6: A3SZ0 0 ...
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Wait Control Register (WCR) Bit Bit name: IW31 IW30 Initial value: 1 R/W: R/W R/W Bit: 7 Bit name: W31 W30 Initial value: 1 R/W: R/W R/W Do not access a space other than CS0 until the ...
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When area 3 is DRAM, the number of CAS assert cycles is specified by wait control bits W31 and W30: Bit 7: W31 Bit 6: W30 When the setting is for 2 or more ...
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Individual Memory Control Register (MCR) Bit Bit name: TRP RCD Initial value: 0 R/W: R/W R/W Bit: 7 Bit name: AMX2 SZ Initial value: 0 R/W: R/W R/W The TRP, RCD, TRWL, TRAS1–TRAS0, BE, RASD, AMX2–AMX0 and ...
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Bit 13—Write-Precharge Delay (TRWL): When the synchronous DRAM is not in the bank active mode, this bit specifies the number of cycles between the write cycle and the start-up of the auto-precharge. The timing from this point to the point ...
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Bit 9—RAS Down Mode (RASD) Bit 9: RASD Description 0 For DRAM, RAS is negated after access ends (normal operation). For synchronous DRAM, a read or write is performed using auto- precharge mode The next access always starts with a ...
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For synchronous DRAM interface: Bit 7: Bit 5: AMX2 AMX1 Note: Reserved. Do not set when SZ bit in MCR is 0 (16-bit bus width). Bit 6—Memory Data Size (SZ): For synchronous DRAM, DRAM, ...
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Bit 2: RMODE Description 0 Normal refresh 1 Self-refresh Bits 8, 1, and 0—Reserved: These bits always read 0. 7.2.5 Refresh Timer Control/Status Register (RTCSR) Bit Bit name: — — Initial value: 0 R/W: R Bit: 7 Bit ...
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Bits 5 to 3—Clock Select Bits (CKS2–CKS0) Bit 5: CKS2 Bit 4: CKS1 Bits 2 to 0—Reserved: These bits always read 0. The write value should always be 0. 7.2.6 Refresh Timer Counter (RTCNT) ...
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Refresh Time Constant Register (RTCOR) Bit Bit name: — — Initial value: 0 R/W: R Bit: 7 Bit name: Initial value: 0 R/W: R/W R/W RTCOR is an 8-bit read/write register. The values of RTCOR and RTCNT ...
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Instruction fetches are always performed in 32-bit units. When branching to an odd word boundary ( address), instruction fetches are performed in longword units from a 4n address. Figures 7.2 to 7.4 show the relationship between device data ...
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Connection to Little-Endian Devices The SH7604 provides a conversion function in CS2 space for connection to and to maintain program compatibility with devices that use little-endian format (in which the LSB is the 0 position in the byte data ...
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D15 A26–A0 000000 7 000001 000002 7 000003 000000 7 000002 7 000000 7 16 000002 23 Figure 7.6 16-Bit External Devices and Their Access Units (Little-Endian Format) Using the Little-Endian Function: The SH7604 normally uses big-endian alignment for data ...
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A26–A0 RD/WR Read D31–D0 Write D31–D0 Figure 7.7 Basic Timing of Ordinary Space Access Figure ...
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SH7604 A18 A2 CSn RD D31 D24 CASHH/DQMUU/WE3 D23 D16 CASHL/DQMUL/WE2 D15 D8 CASLH/DQMLU/WE1 D7 D0 CASLL/DQMLL/WE0 Figure 7.8 Example of 32-Bit Data Width SRAM Connection 128 k 8-bit SRAM A16 I/O7 I/O0 WE A16 A0 CS ...
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SH7604 A17 A1 CSn RD D15 D8 CASLH/DQMLU/WE1 D7 D0 CASLL/DQMLL/WE0 Figure 7.9 Example of 16-Bit Data Width SRAM Connection SH7604 A16 A0 CSn CASLL/DQMLL/WE0 Figure 7.10 Example of 8-Bit Data Width SRAM Connection 154 128 k ...
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Wait State Control The number of wait states inserted into ordinary space access states can be controlled using the WCR and BCR1 register settings. When the Wn1 and Wn0 wait specification bits in WCR for the given CS space ...
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When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 7.12 shows WAIT signal sampling. A 2-cycle wait is specified as a software wait. The sampling is performed when the Tw ...
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Synchronous DRAM Interface 7.5.1 Synchronous DRAM Direct Connection 2-Mbit (128k 16), 4-Mbit (256k 16), and 16-Mbit (1M 16 and 4M 4) synchronous DRAMs can be connected directly to the SH7604 All of these are internally divided into ...
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SH7604 A11 A2 CKIO CKE CSn RAS/CE CAS/OE RD/WR D31 D16 CASHH/DQMUU/WE3 CASHL/DQMUL/WE2 D15 D0 CASLH/DQMLU/WE1 CASLL/DQMLL/WE0 Figure 7.13 Synchronous DRAM 32-bit Device Connection 158 256 k 16-bit synchronous DRAM A9 A0 CLK CKE CS RAS CAS WE I/O15 I/O0 ...
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SH7604 A10 A1 CKIO CKE CSn RAS/CE CAS/OE RD/WR D15 D0 CASLH/DQMLU/WE1 CASLL/DQMLL/WE0 Figure 7.14 Synchronous DRAM 16-bit Device Connection 7.5.2 Address Multiplexing Addresses are multiplexed according to the MCR’s address multiplex specification bits AMX2– AMX0 and size specification bit ...
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Table 7.4 SZ and AMX Bits and Address Multiplex Output Setting SZ AMX2 AMX1 AMX0 Output Timing Column address Row address Column address Row address Column address Row ...
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Figure 7.15 shows an example of the basic cycle. Because a slower synchronous DRAM is connected, setting WCR and MCR bits can extend the cycle. The number of cycles from the ACTV command output cycle Tr to the READA command ...
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Tr Tc CKIO A26–A11 A10 A9–A1 CS2 or CS3 RAS CAS WE DQMxx D31–D0 BS Figure 7.15 Basic Burst Read Timing (Auto-Precharge) 162 Td1 Td2 Td3 Td4 Tap ...
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Tr TrW CKIO A26–A11 A10 A9–A1 CS2 or CS3 RAS CAS WE DQMxx D31–D0 BS Figure 7.16 Burst Read Wait Specification Timing (Auto-Precharge Td1 Td2 Td3 Td4 Tap 163 ...
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Single Reads When a cache area is accessed and there is a cache miss, the cache fill cycle is performed in 16- byte units. This means that all the data read in the burst read is valid. Since the ...
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Tr Tc CKIO A26–A11 A10 A9–A1 CS2 or CS3 RAS CAS WE DQMxx D31–D0 BS Figure 7.17 Single Read Timing (Auto-Precharge) 7.5.5 Writes Unlike synchronous DRAM reads, synchronous DRAM writes are single writes. Figure 7.18 shows the basic timing chart ...
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Tr CKIO A26–A11 A10 A9–A1 CS2 or CS3 RAS CAS WE DQMxx D31–D0 BS Figure 7.18 Basic Write Cycle Timing (Auto-Precharge) 7.5.6 Bank Active Function A synchronous DRAM bank function is used to support high-speed accesses of the same row ...
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ACTV command and READ or WRIT command, in that order, after the precharge is completed. With successive accesses to different row addresses, the precharge is performed after the access request occurs, so the access time is longer. When writing, performing ...
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Tr Tc CKIO A26–A11 A10 A9–A1 CS3 RAS CAS WE DQMxx D31–D0 BS Figure 7.19 Burst Read Timing (No Precharge) 168 Td1 Td2 Td3 Td4 ...
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Tnop Tc CKIO A26–A11 A10 A9–A1 CS3 RAS CAS WE DQMxx D31–D0 BS Figure 7.20 Burst Read Timing (Bank Active, Same Row Address) Td1 Td2 Td3 Td4 169 ...
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Tp Tr CKIO A26–A11 A10 A9–A1 CS3 RAS CAS WE DQMxx D31–D0 BS Figure 7.21 Burst Read Timing (Bank Active, Different Row Addresses) 170 Tc Td1 Td2 Td3 Td4 ...
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Tr Tc CKIO A26–A11 A10 A9–A1 CS3 RAS CAS WE DQMxx D31–D0 BS Figure 7.22 Write Timing (No Precharge) 171 ...
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CKIO A26–A11 A9–A1 DQMxx D31–D0 Figure 7.23 Write Timing (Bank Active, Same Row Address) 172 Tc A10 CS3 RAS CAS WE BS ...
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Tp CKIO A26–A11 A10 A9–A1 CS3 RAS CAS WE DQMxx D31–D0 BS Figure 7.24 Write Timing (Bank Active, Different Row Addresses 173 ...
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Refreshes The bus state controller is equipped with a function to control refreshes of synchronous DRAM. Auto-refreshes can be performed by setting the MCR’s RMD bit to 0 and the RFSH bit to 1. When the synchronous DRAM is ...
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Tp Trr CKIO A10 CS2 or CS3 RAS CAS WE DQMxx BS Figure 7.25 Auto-Refresh Timing Self-Refreshes: The self-refresh mode is a type of standby mode that produces refresh timing and refresh addresses within the synchronous DRAM started ...
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Refresh Requests and Bus Cycle Requests: When a refresh request occurs while a bus cycle is executing, the refresh will not be executed until the bus cycle is completed. When a refresh request occurs while the bus is released using ...
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Power-On Sequence To use synchronous DRAM, the mode must first be set after the power is turned on. To properly initialize the synchronous DRAM, the synchronous DRAM mode register must be written to after the registers of the bus ...
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CKIO A26–A12 A11 A10 A9–A1 CS2 or CS3 RAS CAS WE DQMxx BS Figure 7.27 Synchronous DRAM Mode Write Timing 178 Tp Tmw ...
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Phase Shift by PLL The signals for synchronous DRAM interfaces change in the SH7604 at the rising edge of the internal clock. Read data is fetched on the falling edge of an internal clock. Sampling of the signals input ...
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Phase Shifted 90 by PLL External CLK (CKIO) Internal CLK Signal output b. Phase Shift Using PLL is 0 External CLK (CKIO) Internal CLK Signal output Figure 7.28 Phase Shift by PLL 180 1/4 cycle (90 ) 3/4 cycle ...
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No PLL Used External CLK (CKIO) Clock circut delay Internal CLK Signal output Figure 7.28 Phase Shift by PLL (cont) 7.6 DRAM Interface 7.6.1 DRAM Direct Connection When the DRAM and other memory enable bits (DRAM2–DRAM0) in BCR1 are ...
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SH7604 A10 A2 RAS/CE RD/WR D31 D16 CASHH/DQMUU/WE3 CASHL/DQMUL/WE2 D15 D0 CASLH/DQMLU/WE1 CASLL/DQMLL/WE0 Figure 7.29 Example of DRAM Connection (32-Bit Data Width) 182 256k 16 bit DRAM A8 A0 RAS OE WE I/O15 I/O0 UCAS LCAS A8 A0 RAS OE ...
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SH7604 A9 A1 RAS/CE RD/WR D15 D0 CASLH/DQMLU/WE1 CASLL/DQMLL/WE0 Figure 7.30 Example of DRAM Connection (16-Bit Data Width) 7.6.2 Address Multiplexing When the CS3 space is set to DRAM, addresses are always multiplexed. This allows DRAMs that require multiplexing of ...
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Basic Timing The basic timing of a DRAM access is 3 cycles. Figure 7.31 shows the basic DRAM access timing the precharge cycle the RAS assert cycle, Tc1 is the CAS assert cycle, and Tc2 ...