HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet
HD6473258P10
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HD6473258P10 Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Hitachi Single-Chip Microcomputer H8/325 Series H8/3257, H8/3256 H8/325, H8/324, H8/323, H8/322 Hardware Manual ...
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The H8/325 Series is a family of high-performance single-chip microcomputers ideally suited for embedded control of industrial equipment. The chips are built around an H8/300 CPU core: a high- speed processor. On-chip supporting modules provide ROM, RAM, two types of ...
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Section 1. Overview ............................................................................................................... 1.1 Overview............................................................................................................................... 1.2 Block Diagram...................................................................................................................... 1.3 Pin Assignments and Functions............................................................................................ 1.3.1 Pin Arrangement...................................................................................................... 1.3.2 Pin Functions ........................................................................................................... Section 2. MCU Operating Modes and Address Space 2.1 Overview............................................................................................................................... 15 2.2 Mode Descriptions................................................................................................................ 16 2.3 Address Space Map ...
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Block Data Transfer Instruction .............................................................................. 52 3.6 CPU States ............................................................................................................................ 54 3.6.1 Program Execution State ......................................................................................... 55 3.6.2 Exception-Handling State........................................................................................ 55 3.6.3 Power-Down State ................................................................................................... 56 3.7 Access Timing and Bus Cycle .............................................................................................. 56 3.7.1 Access to On-Chip Memory ...
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Section 6. Parallel Handshaking Interface 6.1 Overview............................................................................................................................... 113 6.1.1 Features.................................................................................................................... 113 6.1.2 Block Diagram......................................................................................................... 114 6.1.3 Input and Output Pins .............................................................................................. 115 6.1.4 Register Configuration ............................................................................................ 115 6.2 Register Descriptions............................................................................................................ 115 6.2.1 Port 3 Data Direction Register (P3DDR) ................................................................ 115 ...
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Setting of FRC Overflow Flag (OVF)..................................................................... 141 7.5 Interrupts............................................................................................................................... 142 7.6 Noise Canceler...................................................................................................................... 142 7.7 Sample Application............................................................................................................... 144 7.8 Application Notes ................................................................................................................. 145 Section 8. 8-Bit Timers 8.1 Overview............................................................................................................................... 151 8.1.1 Features.................................................................................................................... 151 8.1.2 Block Diagram......................................................................................................... 151 8.1.3 Input ...
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Serial Mode Register (SMR) – H’FFD8.................................................................. 173 9.2.6 Serial Control Register (SCR) – H’FFDA............................................................... 175 9.2.7 Serial Status Register (SSR) – H’FFDC.................................................................. 177 9.2.8 Bit Rate Register (BRR) – H’FFD9 ........................................................................ 179 9.3 Operation .............................................................................................................................. 183 9.3.1 Overview ................................................................................................................. ...
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Exit from Sleep Mode ............................................................................................. 222 12.4 Software Standby Mode........................................................................................................ 222 12.4.1 Transition to Software Standby Mode..................................................................... 223 12.4.2 Exit from Software Standby Mode.......................................................................... 223 12.4.3 Sample Application of Software Standby Mode ..................................................... 223 12.4.4 Notes on Current Dissipation ...
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Appendices Appendix A. CPU Instruction Set A.1 Instruction Set List................................................................................................................ 257 A.2 Operation Code Map............................................................................................................. 264 A.3 Number of States Required for Execution............................................................................ 266 Appendix B. Register Field B.1 Register Addresses and Bit Names....................................................................................... 272 B.2 Register Descriptions............................................................................................................ 276 Appendix ...
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Overview The H8/325 Series is a series of single-chip microcomputers integrating a CPU core together with a variety of peripheral functions needed in control systems. The H8/300 CPU is a high-speed processor featuring powerful bit-manipulation instructions, ideally suited for ...
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Table 1-1 lists the features of the H8/325 Series. Table 1-1. Features Feature Description CPU General register architecture • Eight 16-bit general registers, or • Sixteen 8-bit general registers High speed • Maximum clock rate: 10 MHz • Add/subtract: • ...
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Table 1-1. Features (cont.) Feature Description Serial communi- • Selection of asynchronous and synchronous modes cation interface • Simultaneous transmit and receive (full duplex operation) (SCI: 2 channels) • On-chip baud rate generator I/O ports • 53 input/output pins (of ...
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Table 1-1. Features (cont.) Feature Description Product lineup Type code (cont.) (5V series) HD6473258C HD6473258P HD6473258F HD6473258CP HD6433258P HD6433258F HD6433258CP HD6413258P HD6413258F HD6413258CP HD6433248P HD6433248F HD6433248CP HD6473238P HD6473238F HD6473238CP HD6433238P HD6433238F HD6433238CP HD6413238P HD6413238F HD6413238CP HD6473228P HD6473228F HD6473228CP HD6433228P HD6433228F ...
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Block Diagram Figure 1-1 shows a block diagram of the H8/325 Series ...
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Pin Assignments and Functions 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8/325 Series in the DC-64S and DP-64S packages. Figure 1-3 shows the pin arrangement in the FP-64A package. Figure 1-4 shows the pin arrangement ...
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XTAL 1 EXTAL NMI STBY /TMCI /TMO /TMRI /TMCI 3 1 ...
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PLCC-68 XTAL 10 EXTAL NMI STBY /TMCI /TMO /TMRI ...
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Table 1-2. Pin Assignments in Each Operating Mode (1) Pin no. DC-64S DP-64S FP-64A CP-68 — — ...
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Table 1-2. Pin Assignments in Each Operating Mode (1) Pin no. DC-64S DP-64S FP-64A CP- — — ...
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Table 1-2. Pin Assignments in Each Operating Mode (1) Pin no. DC-64S DP-64S FP-64A CP- ...
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Pin Functions: Table 1-3 gives a concise description of the function of each pin. Table 1-3. Pin Functions (1) Type Symbol I/O Power Clock XTAL I EXTAL I Ø System ...
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Table 1-3. Pin Functions (2) Type Symbol I/O Bus IOS O control Interrupt NMI I signals IRQ IRQ 2 Operating mode MD 0 control 16-Bit free- FTCI I running timer FTOA, O FTOB ...
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Table 1-3. Pin Functions (3) Type Symbol Serial com- TxD 0 munication TxD 1 interface RxD 0 RxD 1 SCK 0 SCK 1 General purpose I ...
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Section 2. MCU Operating Modes and Address Space 2.1 Overview The H8/325 Series operates in three modes numbered 1, 2, and 3. An additional non-operating mode (mode 0) is used for programming the PROM version of the H8/325. The mode ...
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Mode Descriptions Mode 1 (Expanded Mode without On-Chip ROM): Mode 1 supports a 64-kbyte address space most of which is off-chip. In particular, the interrupt vector table is located in off-chip memory. The on-chip ROM is not used. Software ...
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External memory is accessed a byte at a time in three or more states. The basic bus cycle is three states, but additional wait states can be inserted on request. 2.3.2 IOS There are two gaps in the on-chip address ...
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Mode 1 Expand mode without on-chip ROM H'0000 Vector table H'002F H'0030 External address space H'F77F H'F780 On-chip RAM*, 2 Kbytes H'FF7F H'FF80 External address space H'FF8F H'FF90 On-chip register field H'FF9F H'FFA0 External address space H'FFAF H'FFB0 On-chip register ...
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Mode 1 Expand mode without on-chip ROM H'0000 Vector table H'002F H'0030 External address space H'F77F H'F780 On-chip RAM*, 2 Kbytes H'FF7F H'FF80 External address space H'FF8F H'FF90 On-chip register field H'FF9F H'FFA0 External address space H'FFAF H'FFB0 On-chip register ...
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Mode 1 Expand mode without on-chip ROM H'0000 Vector table H'002F H'0030 External address space H'FB7F H'FB80 On-chip RAM*, 1 Kbyte H'FF7F H'FF80 External address space H'FF8F H'FF90 On-chip register field H'FF9F H'FFA0 External address space H'FFAF H'FFB0 On-chip register ...
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Mode 1 Expand mode without on-chip ROM H'0000 Vector table H'002F H'0030 External address space H'FB7F H'FB80 *1 On-chip RAM, 1 Kbyte H'FF7F H'FF80 External address space H'FF8F H'FF90 On-chip register field H'FF9F H'FFA0 External address space H'FFAF H'FFB0 On-chip ...
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Mode 1 Expand mode without on-chip ROM H'0000 Vector table H'002F H'0030 External address space H'FD7F H'FD80 On-chip RAM*, 512 bytes H'FF7F H'FF80 External address space H'FF8F H'FF90 On-chip register field H'FF9F H'FFA0 External address space H'FFAF H'FFB0 On-chip register ...
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Mode 1 Expand mode without on-chip ROM H'0000 Vector table H'002F H'0030 External address space H'FD7F H'FD80 *1 *2 Reserved H'FE7F H'FE80 *1 On-chip RAM, 256 bytes H'FF7F H'FF80 External address space H'FF8F H'FF90 On-chip register field H'FF9F H'FFA0 External ...
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Mode and System Control Registers (MDCR and SYSCR) Two of the control registers in the register field are the mode control register (MDCR) and system control register (SYSCR). The mode control register controls the MCU mode: the operating mode ...
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System Control Register (SYSCR)—H’FFC4 By setting or clearing bit 0 of the system control register, software can enable or disable the on-chip RAM. The other bits in the system control register concern the software standby mode and the valid ...
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Overview The H8/325 Series has the generic H8/300 CPU: an 8-bit central processing unit with a speed- oriented architecture featuring sixteen general registers. This section describes the CPU features and functions, including a concise description of the addressing modes ...
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Register Configuration Figure 3-1 shows the register structure of the CPU. There are two groups of registers: the general registers and control registers. 7 R0H R1H R2H R3H R4H R5H R6H R7H 15 3.2.1 General Registers All the general ...
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SP (R7) 3.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). (1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. ...
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Bit 2—Zero (Z): This bit is set to “1” to indicate a zero result and cleared to “0” to indicate a nonzero result. Bit 1—Overflow (V): This bit is set to “1” when an arithmetic overflow occurs, and cleared to ...
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Addressing Modes The H8/325 supports eight addressing modes. Each instruction uses a subset of these addressing modes. (1) Register Direct—Rn: The register field of the instruction specifies 16-bit general register containing the operand. In most cases ...
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Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the ...
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Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. • Bit manipulation instructions operate on 1-bit data specified as bit ..., 7) in ...
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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 3-3. Data type 1-Bit data 1-Bit data Byte data Byte data Word data 4-Bit BCD data 4-Bit BCD ...
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Memory Data Formats Figure 3-4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as “0.” ...
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Instruction Set Table 3-1 lists the H8/325 Series instruction set. Table 3-1. Instruction Classification Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer *1 PUSH Rn is equivalent to MOV.W Rn, @–SP. ...
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Operation Notation Rd General register (destination) Rs General register (source) Rn, Rm General register General register field n m <EAs> Effective address: general register or memory location (EAd) Destination operand (EAs) Source operand SP Stack pointer PC ...
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Data Transfer Instructions Table 3-2 describes the data transfer instructions. Figure 3-5 shows their object code formats. Table 3-2. Data Transfer Instructions Instruction Size* B/W MOV B MOVTPE B MOVFPE W PUSH W POP * Size: operand size B: ...
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disp abs #imm. Op abs. Op Notation Op: Operation field d: Direction field (0–load from; 1–store to Register field disp.: ...
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Arithmetic Operations Table 3-3 describes the arithmetic instructions. See figure 3-6 in section 3.5.4, “Shift Operations” for their object codes. Table 3-3. Arithmetic Instructions Instruction Size* B/W ADD SUB B ADDX SUBX B INC DEC W ADDS SUBS B ...
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Logic Operations Table 3-4 describes the four instructions that perform logic operations. See figure 3-6 in section 3.5.4, “Shift Operations” for their object codes. Table 3-4. Logic Operation Instructions Instruction Size* B AND XOR B NOT ...
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Notation Op: Operation field Register field #imm.: Immediate data Figure 3-6. Arithmetic, Logic, and Shift Instruction Codes ...
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Bit Manipulations Table 3-6 describes the bit-manipulation instructions. Figure 3-7 shows their object code formats. Table 3-6. Bit-Manipulation Instructions (1) Instruction Size* B BSET B BCLR B BNOT B BTST B BAND BIAND B BOR BIOR B BXOR * ...
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Table 3-6. Bit-Manipulation Instructions (2) Instruction Size* B BIXOR B BLD BILD B BST BIST * Size: operand size B: Byte Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-modify- write instructions. They read a byte ...
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Before Execution of BCLR Instruction P4 7 Input/output Input Pin state Low DDR Pull-up Mos On Execution of BCLR Instruction BCLR.B #0, @P4DDR After Execution of BCLR Instruction P4 7 Input/output Output Output Output Output Output Output ...
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Before Execution of BSET Instruction P4 7 Input/output Input Pin state Low DDR Pull-up Mos On Execution of BSET Instruction BSET.B #0, @PORT4 After Execution of BSET Instruction P4 7 Input/output Input Pin state Low DDR 0 ...
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Before Execution of BSET Instruction MOV.B #80, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PORT4 P4 7 Input/output Input Pin state Low DDR Pull-up Mos On RAM0 1 Execution of BSET Instruction BSET.B #0, @RAM0 After Execution of ...
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Notation Op: Operation field Register field abs.: Absolute address #imm.: Immediate data ...
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Branching Instructions Table 3-7 describes the branching instructions. Figure 3-8 shows their object code formats. Table 3-7. Branching Instructions Instruction Size — Bcc — JMP — JSR — BSR — RTS Function Branches if condition cc is true. Mnemonic ...
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Notation Op: Operation field cc: Condition field Register field disp.: Displacement abs.: Absolute address Figure 3-8. Branching Instruction Codes 8 7 disp abs. ...
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System Control Instructions Table 3-8 describes the system control instructions. Figure 3-9 shows their object code formats. Table 3-8. System Control Instructions Instruction Size — RTE — SLEEP B LDC B STC B ANDC B ORC B XORC — ...
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Op Notation Op: Operation field Register field #imm.: Immediate data Figure 3-9. System Control Instruction Codes 3.5.8 Block Data Transfer Instruction Table 3-9 describes the EEPMOV instruction. Figure 3-10 shows its object code format. Table 3-9. ...
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Figure 3-10. Block Data Transfer Instruction/EEPROM Write Operation Code Notes on EEPMOV Instruction Note 1 • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by ...
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Phenomenon — H8/300 CPU will malfunction after EEPMOV instruction execution. • Counter Measures by Software or Circuitry Please take at least one counter measure from the followings. — Please use EEPMOV when the destination is in the internal area ...
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Interrupt request Exception - handling state RES = 1 Reset state Notes transition to the reset state occurs when RES goes Low, except when the chip is in the hardware standby mode transition from any state ...
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Power-Down State The power-down state includes three modes: the sleep mode, the software standby mode, and the hardware standby mode. (1) Sleep Mode: The sleep mode is entered when a SLEEP instruction is executed. The CPU halts, but CPU ...
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Internal address bus Internal Read signal Internal data bus (read) Internal Write signal Internal data bus (write) Figure 3-13. On-Chip Memory Access Cycle Ø Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 3-14. ...
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Access to On-Chip Register Field and External Devices The on-chip register field (I/O ports, dual-port RAM, on-chip supporting module registers, etc.) and external devices are accessed in a cycle consisting of three states: T data can be accessed per ...
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Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 3-16. Pin States during On-Chip Register Field Access Cycle Ø Address bus AS RD WR: High Data bus Figure 3-17 (a). External Device Access Timing ...
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T1 state Ø Address bus AS RD: High WR Data bus Figure 3-17 (b). External Device Access Timing (write) Write cycle T2 state T3 state Address Write data Fig. 3-17 (b) 60 ...
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Section 4. Exception Handling 4.1 Overview The H8/325 Series recognizes only two kinds of exceptions: interrupts and the reset. Table 4-1 indicates their priority and the timing of their hardware exception-handling sequence. The ROMless versions (HD6413258, HD6413238) are used only ...
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The value at the mode pins (MD control register (MDCR). (2) In the condition code register (CCR), the I bit is set mask interrupts. (3) The registers of the I/O ports and on-chip supporting modules are ...
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Figure 4-2. Reset Sequence (Mode 1) 63 Figure. 4-2 ...
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Disabling of Interrupts after Reset All interrupts, including NMI, are disabled immediately after a reset. The first program instruction, located at the address specified at the top of the vector table, is therefore always executed. To prevent program crashes, ...
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Table 4-2. Interrupts Interrupt source NMI IRQ 0 IRQ 1 IRQ 2 Port ISI (Input strobe) 16-Bit free- ICI (Input capture) running timer OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) 8-Bit timer 0 CMI0A (Compare-match A) CMI0B ...
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Table 4-3. Registers Read by Interrupt Controller Name System control register IRQ sense control register IRQ enable register (1) System Control Register (SYSCR)—H’FFC4 Bit 7 SSBY Initial value 0 Read/Write R/W Bit 2 (NMIEG) is the only bit read by ...
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Bit 2 Bit 6 IRQ SC IRQ Bits 5 and 1—IRQ Sense Control (IRQ 1 the IRQ pin is sensed. 1 Bit 1 Bit 5 IRQ SC IRQ EG ...
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Bit IRQiE Description 0 IRQi is disabled. 1 IRQi is enabled. Edge-sensed interrupt signals are latched (if enabled) and held until the interrupt is served. They are latched even if the interrupt mask bit ...
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Internal Interrupts Seventeen internal interrupts can be requested by the on-chip supporting modules. All of them are masked when the I bit in the CCR is set. In addition, they can all be enabled or disabled by bits in ...
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Note: Interrupt requests are not detected immediately after the ANDC, ORC, XORC, and LDC instructions. 4.3.5 Interrupt Handling Figure 4-3 shows a block diagram of the interrupt controller. Figure 4 flowchart showing the operation of the interrupt controller ...
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The timing of this sequence is shown in figure 4-6 for the case in which the program and vector table are in on-chip ROM and the stack is in on-chip RAM. NMI interrupt IRQ flag 0 IRQ E 0 IRQ ...
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Program execution Interrupt request present NMI ? Y N IRQ ? 0 Y IRQ ? 1 Y I=0 in CCR? Y Save PC Save CCR I 1, masking all interrupts except NMI To software interrupt-handling routine Figure 4-4. ...
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SP-4 SP-3 SP-2 SP-1 SP(R7) Stack area Before interrupt is accepted PC : Program counter CCR : Condition code register SP : Stack pointer * Ignored on return. : Notes: 1. The PC contains the address of the first instruction ...
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Interrupt accepted Interrupt priority decision. Wait for end of instruction. Interrupt request signal Ø Internal address (1) bus Internal Read signal Internal Write signal Internal 16-bit (2) data bus (1) Instruction prefetch address (Pushed on stack. Instruction is executed on ...
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Interrupt Response Time Table 4-4 indicates the time that elapses from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since the H8/325 Series accesses its on-chip memory 16 bits at a time, ...
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SP BSR instruction H'FEFF set Upper byte of program counter Lower byte of program counter General register Stack pointer Figure 4-7. Example of Damage Caused by Setting ...
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Overview The H8/325 Series has seven parallel I/O ports, including: • Five 8-bit input/output ports—ports and 7 • One 7-bit input/output port—port 6 • One 6-bit input/output port—port 5 All ports have programmable MOS input ...
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Table 5-1. Auxiliary Functions of Input/Output Ports I/O Port Auxiliary functions Port 1 Address bus (low) Port 2 Address bus (high) Port 3 Data bus or parallel handshaking data lines Port 4 System clock and E clock output, 8-bit timer ...
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Table 5-3 details the port 1 registers. Table 5-3. Port 1 Registers Name Port 1 data direction register Port 1 data register Port 1 Data Direction Register (P1DDR)—H’FFB0 Bit 7 P1 DDR P1 7 Mode 1 Initial value 1 Read/Write ...
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Mode 2: In mode 2 (expanded mode with on-chip ROM), the usage of port 1 can be selected on a pin-by-pin basis. A pin is used for general-purpose input if its data direction bit is cleared for ...
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Hardware standby P1 n 5.3 Port 2 Port 8-bit input/output port that also provides the high bits of the address bus. The function of port 2 depends on the MCU mode as indicated in table 5-4. Table ...
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Pins of port 2 can drive a single TTL load and a 90-pF capacitive load when they are used as output pins. They can also drive light-emitting diodes or a Darlington pair. Table 5-5 details the port 2 registers. Table ...
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Mode 1: In mode 1 (expanded mode without on-chip ROM), port 2 is automatically used for address output. The port 2 data direction register is unwritable. All bits in P2DDR are automatically set to 1 and cannot be cleared to ...
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Hardware standby P2 n 5.4 Port 3 Port 8-bit input/output port that also provides the external data bus and data pins for the parallel handshaking interface. The function of port 3 depends on the MCU mode as ...
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They can also drive a Darlington pair. Table 5-7 details the port 3 registers. Table 5-7. Port 3 Registers Name Port 3 data direction register Port 3 data register Port 3 Data Direction Register (P3DDR)—H’FFB4 Bit 7 P3 DDR ...
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Input Latches: All pins of port 3 have input latches which can be enabled by the LTE bit in the handshake control/status register (HCSR) in mode 3. When the LTE bit is set to 1, input data are latched on ...
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P3 n WP3D: Write Port 3 DDR WP3: Write Port 3 RP3: Read Port 5.5 Port 4 Port 8-bit input/output port that also provides input and output pins for the 8-bit ...
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Table 5-8. Port 4 Pin Functions Usage Pin Functions I/O port P4 0 Timer or clock TMCI 0 See section 8, 8-Bit Timer Module for details of the timer output select bits. Pins of port 4 can drive a single ...
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Port 4 Data Register (P4DR)—H’FFB7 Bit Initial value 0 Read/Write R/W P4DR is an 8-bit register containing output data for pins P4 ups. When the CPU reads P4DR, for output pins (P4DDR = 1) it reads the ...
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Reset: P4DDR and P4DR and the 8-bit timer control registers are initialized, making pins P4 P4 into input port pins with the MOS pull-ups off. When the chip comes out of reset into single- 5 chip mode (mode 3), P4 ...
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P4 n WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port Figure 5-4. Port 4 Schematic Diagram (Pins P4 Reset DDR n C WP4D Reset R ...
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P4 n WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port Figure 5-5. Port 4 Schematic Diagram (Pins P4 Reset DDR n C WP4D Reset ...
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Hardware standby P4 6 WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port 4 Figure 5-6. Port 4 Schematic Diagram (Pin P4 Mode Reset DDR 6 C WP4D Reset R ...
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Hardware standby P4 7 WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port 4 Figure 5-7. Port 4 Schematic Diagram (Pin P4 5.6 Port 5 Port 6-bit input/output port that also provides the input ...
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See section 9, Serial Communication Interface for details of the serial control bits. Pins used by the serial communication interface are switched between input and output without regard to the values in the data direction register. Pins of port 5 ...
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Pins P5 and P5 : These pins can be used for general-purpose input or output, or for output serial transmit data (TxD). When used for TxD output, these pins are unaffected by the values in P5DDR and ...
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P5 n WP5D: Write Port 5 DDR WP5: Write Port 5 RP5: Read Port Figure 5-8. Port 5 Schematic Diagram (Pins P5 Reset DDR n C WP5D Reset ...
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P5 n WP5D: Write Port 5 DDR WP5 Write Port 5 RP5: Read Port Figure 5-9. Port 5 Schematic Diagram (Pins P5 Reset DDR n C WP5D Reset ...
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P5 n WP5D: Write Port 5 DDR WP5: Write Port 5 RP5: Read Port Figure 5-10. Port 5 Schematic Diagram (Pins P5 5.7 Port 6 Port 7-bit input/output port that also provides ...
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Table 5-12. Port 6 Pin Functions Usage Pin functions (Modes I/O port P6 0 Timer/interrupt FTCI See section 4, Exception Handling and section 7, Free-Running Timer Module for details of the free-running timer and interrupts. Pins of ...
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MOS Pull-Ups: Are available for input pins, including pins used for input of timer or interrupt signals. Software can turn the MOS pull- writing P6DR, and turn it off by writing a 0. The pull-ups ...
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P6 n WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port Figure 5-11. Port 6 Schematic Diagram (Pins P6 Reset DDR n C WP6D Reset ...
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P6 n WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port Figure 5-12. Port 6 Schematic Diagram (Pins P6 Reset DDR n C WP6D Reset ...
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P6 n WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port Figure 5-13. Port 6 Schematic Diagram (Pins P6 5.8 Port 7 Port 8-bit input/output port that also ...
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Table 5-14. Port 7 Pin Functions Pin Expanded modes P7 P7 input/output or IS input input/output input/output input or IOS output output 4 P7 ...
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P7DR is an 8-bit register containing output data for pins P7 ups. When the CPU reads P7DR, for output pins (P7DDR = 1) it reads the value in the P7DR latch, but for input pins (P7DDR = 0), it obtains ...
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In mode 3 (single-chip mode), this pin can be used for general-purpose input or output. Reset: In the single-chip mode (mode 3), a reset initializes all pins of port 7 to the general-purpose input state with the MOS pull-ups off. ...
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P7 0 WP7D: Write Port 7 DDR WP7: Write Port 7 RP7: Read Port 7 Figure 5-14. Port 7 Schematic Diagram (Pin WP7D Q P7 WP7 RP7 0 108 Reset R D DDR 0 C Reset R ...
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P7 n WP7D: Write Port 7 DDR WP7: Write Port 7 RP7 : Read Port Figure 5-15. Port 7 Schematic Diagram (Pins P7 Reset DDR n C WP7D Reset R D ...
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P7 3 Mode WP7D: Write Port 7 DDR WP7: Write Port 7 RP7: Read Port 7 Figure 5-16. Port 7 Schematic Diagram (Pin P7 Mode 3 110 Reset DDR 3 C WP7D Reset ...
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Hardware standby P7 n Mode WP7D: Write Port 7 DDR WP7: Write Port 7 RP7: Read Port Figure 5-17. Port 7 Schematic Diagram (Pins P7 Mode Mode 3 ...
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Mode WP7D: Write Port 7 DDR WP7: Write Port 7 RP7: Read Port 7 Figure 5-18. Port 7 Schematic Diagram (Pin P7 Reset DDR 7 C WP7D Reset ...
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Section 6. Parallel Handshaking Interface 6.1 Overview In single-chip mode (mode 3), the H8/325 Series chips can interface to another device by parallel handshaking, using port 3. 6.1.1 Features • Built-in latch circuits Data input to port 3 can be ...
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Block Diagram Figure 6 block diagram of the parallel handshaking interface. OS BUSY IS ISI interrupt signal P3 n WP3: Write Port 3 RP3: Read Port 3 WP3D: Write Port 3 DDR n =0 to7 Figure 6-1. ...
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Input and Output Pins Table 6-1 lists the input and output pins used by the parallel handshaking interface. Table 6-1. Input and Output Pins of Parallel Handshaking Interface Name Data input/output pins Input strobe Output strobe Busy 6.1.4 Register ...
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Port 3 Data Register (P3DR) Bit Initial value 0 Read/Write R/W When the parallel handshaking interface is used for output (P3DDR = H'FF), P3DR stores the output data. If port 3 is read, the P3DR data ...
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Bit 6—Input Strobe Interrupt Enable (ISIE): Enables or disables the handshake interrupt request (ISI). Bit 6 ISIE Description 0 The handshake interrupt request (ISI) is disabled. 1 The handshake interrupt request (ISI) is enabled. Bit 5—Output Strobe Enable (OSE): Enables ...
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Bit 2—Busy Enable (BSE): This bit enables or disables output of the busy signal. Do not set BSE the expanded modes (modes 1 and 2). Bit 2 ISIE Description 0 Busy signal output is disabled. 1 Busy ...
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Port 3 write Ø Port 3 OS (Consecutive Writing of Port 3 When OSS = 1) 6.3.2 Busy Signal Output Timing The busy signal remains low from the fall of the input strobe signal until the data latched in port ...
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Port 3 write Ø Port 3 OS Figure 6-5. Output Strobe Timing in Software Standby Mode When the ISIE and LTE bits in the handshake control/status register (HCSR) are both set high-to-low transition of the IS ...
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Write Sending H8/325 P3DR Interrupt Receiving H8/325 request H8/325 (sending chip) Figure 6-7. Parallel Handshaking Interface Timing Chart (Example) 1. The sending and receiving H8/325s set their HCSR bits as follows: Sending H8/325: ...
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Section 7. 16-Bit Free-Running Timer 7.1 Overview The H8/325 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free- running counter as a time base. Applications of the FRT module include rectangular-wave output (up to two ...
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Internal clock sources Ø/2 External clock source Ø/8 Ø/32 FTCI Clock select Compare- match A FTOA FTOB FTI Compare- match B Control logic Capture ICI OCIA OCIB FOVI Interrupt signals Legend OCRA: Output Compare Register A OCRB: Output Compare Register ...
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Input and Output Pins Table 7-1 lists the input and output pins of the free-running timer module. Table 7-1. Input and Output Pins of Free-Running Timer Module Name Abbreviation Counter clock input FTCI Output compare A FTOA Output compare ...
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Register Descriptions 7.2.1 Free-Running Counter (FRC) – H’FF92 Bit Initial value Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Write The FRC is ...
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In addition, if the output enable bit (OEA or OEB) in the timer output compare control register (TCR) is set to 1, when the output compare register and FRC values match, the logic level selected by the output level bit ...
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FTIA, FTIB, FTIC, or FTID Figure 7-2. Minimum Input Capture Pulse Width (Noise Canceler Disabled) The input capture register is initialized to H’0000 at a reset and in the standby modes. Note: When input capture is detected, the FRC ...
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Bit 6 OCIBE Description 0 Output compare interrupt request B (OCIB) is disabled. 1 Output compare interrupt request B (OCIB) is enabled. Bit 5 – Output Compare Interrupt A Enable (OCIAE): Selects whether to request output compare interrupt A (OCIA) ...
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Bit 2 OEA Description 0 Output compare A output is disabled. 1 Output compare A output is enabled. Bits 1 and 0 – Clock Select (CKS1 and CKS0): These bits select external clock input or one of three internal clock ...
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Bit 7 ICF Description 0 To clear ICF, the CPU must read ICF after it has been set to 1, then write this bit. 1 This bit is set to 1 when an FTI input signal causes ...
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Bit 4 OVF Description 0 To clear OVF, the CPU must read OVF after it has been set to 1, then write this bit. 1 This bit is set to 1 when FRC changes from H’FFFF to ...
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FRT Noise Canceler Control Register (FNCR) – H’FFFF Bit 7 — Initial value 1 Read/Write — The FNCR is an 8-bit readable/writable register that controls the input capture noise canceler. The FNCR is initialized to H’ reset ...
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These registers are written and read as follows: • Register Write When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when the CPU writes to the lower byte, this byte of ...
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Upper byte write CPU writes Bus interface data H’AA (2) Lower byte write CPU writes Bus interface data H’55 Figure 7-3 (a). Write Access to FRC (When CPU Writes H’AA55) TEMP [H’AA] FRC L FRC TEMP ...
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Upper byte read CPU writes data H’AA (2) Lower byte read CPU writes data H’55 Figure 7-3 (b). Read Access to FRC (When FRC Contains H’AA55) 7.4 Operation 7.4.1 FRC Incrementation Timing The FRC increments on a pulse generated ...
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Prescaler output FRC clock pulse FRC N – 1 Figure 7-4. Increment Timing for Internal Clock Source (2) External Clock Input: Can be selected by the CKS1 and CKS0 bits in the TCR. The FRC increments on the rising ...
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FTCI Figure 7-6. Minimum External Clock Pulse Width 7.4.2 Output Compare Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in the TCSR is output at the output compare pin (FTOA ...
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Internal compare- match A signal FRC Figure 7-8. Clearing of FRC by Compare-Match A 7.4.4 Input Capture Timing (1) Input Capture Timing without Noise Canceler: An internal input capture signal is generated from the rising or falling edge of ...
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Input at FTI pin Internal input capture signal Figure 7-10. Input Capture Timing (1-State Delay Due to ICR Read) (2) Input Capture Timing with Noise Canceler: The noise canceler samples the FTI input, and does generate an internal input ...
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Internal input capture signal ICF FRC ICR 7.4.6 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when the FRC changes from H’FFFF to H’0000. Figure 7-13 shows the timing of this operation. ...
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Interrupts The free-running timer channel can request four types of interrupts: input capture (ICI), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt is requested when the corresponding flag bit is set, provided the corresponding ...
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Sampling signal C FTI D Q input Latch Sampling signal Figure 7-14. Noise Canceler Block Diagram Table 7-4. Sampling Clock Cycle for Various System Clock Frequencies Sampling NCS1 NCS0 clock 0 0 — Ø/ Ø/64 1 ...
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FTI Sampling clock Noise canceler output 7.7 Sample Application In the example below, the free-running timer channel is used to generate two square-wave outputs with a 50% duty factor and arbitrary phase relationship. The programming is as follows: (1) The ...
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Application Notes Application programmers should note that the following types of contention can occur in the free- running timer. (1) Contention between FRC Write and Clear internal counter clear signal is generated during the T state of ...
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Internal address bus Internal write signal FRC clock pulse FRC Figure 7-18. FRC Write-Increment Contention (3) Contention between OCR Write and Compare-Match compare-match occurs during the T state of a write cycle to the lower byte of ...
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Internal address bus Internal write signal FRC OCRA or OCRB Compare-match signal Figure 7-19. Contention between OCR Write and Compare-Match (4) Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, ...
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Table 7-5. Effect of Changing Internal Clock Sources No. Description Low Low: CKS1 and CKS0 are 1 rewritten while both clock sources are low. Low High: CKS1 and CKS0 are 2 rewritten while old clock source is low and new ...
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Table 7-5. Effect of Changing Internal Clock Sources (cont.) No. Description High High: CKS1 and CKS0 are 4 rewritten while both clock sources are high. Timing chart Old clock source New clock source FRC clock pulse N FRC 149 N ...
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Overview The H8/325 series chips include an 8-bit timer module with two channels. Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-match ...
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External clock source TMCI Clock select TMO TMRI Control logic Interrupt signals TCR: Timer Control Register (8 bits) TCSR: Timer Control Status Register (8 bits) TCORA: Time Constant Register A (8 bits) TCORB: Time Constant Register B (8 bits) TCNT: ...
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Register Configuration Table 8-2 lists the registers of the 8-bit timer module. Each channel has an independent set of registers. Table 8-2. 8-Bit Timer Registers Name Timer control register Timer control/status register Timer constant register A Timer constant register ...
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Time Constant Registers A and B (TCORA and TCORB) – H’FFCA and H’FFCB (TMR0), H’FFD2 and H’FFD3 (TMR1) Bit 7 Initial value 1 Read/Write R/W TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually compared with ...
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Bit 7 CMIEB Description 0 Compare-match interrupt request B (CMIB) is disabled. 1 Compare-match interrupt request B (CMIB) is enabled. Bit 6 – Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request compare-match interrupt A (CMIA) when compare-match ...
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Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 8.2.4 Timer Control/Status Register (TCSR) – H’FFC9 ...
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Bit 6 CMFA Description 0 To clear CMFA, the CPU must read CMFA after it has been set to 1, then write this bit. 1 This bit is set to 1 when TCNT = TCORA. Bit 5 ...
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Bit 1 Bit 0 OS1 OS0 Description change when compare-match A occurs Output changes to 0 when compare-match A occurs Output changes to 1 when compare-match A occurs Output inverts (toggles) ...
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External clock source TCNT clock pulse TCNT N – 1 Figure 8-3. Count Timing for External Clock Input Ø TMCI Ø TMCI Figure 8-4. Minimum External Clock Pulse Widths (Example) 8.3.2 Compare Match Timing (1) Setting of Compare-Match Flags ...
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Accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. Figure 8-5 shows the timing of the setting of the compare-match flags. Ø f TCNT ...
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Figure 8-7 shows the timing when the output is set to toggle on compare-match A. Ø Internal compare-match A signal Timer output (TMO) (4) Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR, the timer ...
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External reset input (TMRI) Internal clear pulse TCNT 8.3.4 Setting of TCSR Overflow Flag (1) Setting of TCSR Overflow Flag (OVF): The overflow flag (OVF) is set to 1 when the timer count overflows (changes from H’FF to ...
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OVF 8.4 Interrupts Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding enable bits are set in the TCR ...
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H’FF TCORA TCORB H’00 TMO pin 8.6 Application Notes Application programmers should note that the following types of contention can occur in the 8-bit timer. (1) Contention between TCNT Write and Clear internal counter clear signal is generated ...
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Contention between TCNT Write and Increment timer counter increment pulse is generated during the T state of a write cycle to the timer counter, the write takes priority and the 3 timer counter is not incremented. Figure ...
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Internal address bus Internal write signal TCNT TCORA or TCORB Compare-match signal Figure 8-15. Contention between TCOR Write and Compare-Match (4) Contention between Compare-Match A and Compare-Match B: If identical time constants are written in TCORA ...
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The pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. If clock sources are changed when the old source is high and the new source is low case No. ...
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Table 8-5. Effect of Changing Internal Clock Sources (cont.) No. Description High Low CKS1 and CKS0 are 3 rewritten while old clock source is high and new clock source is low. High High: CKS1 and CKS0 are 4 ...
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Section 9. Serial Communication Interface 9.1 Overview The H8/325 series chips include a serial communication interface module (SCI) with two channels for transferring serial data to and from other chips. Either synchronous or asynchronous communication can be selected. Communication control ...
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Block Diagram RDR RxD RSR TxD SCK RSR: Receive Shift Register RDR: Receive Data Register TSR: Transmit Shift Register TDR: Transmit Data Register SMR: Serial Mode Register SCR: Serial Control Register SSR: Serial Status Register BRR: Bit Rate Register ...
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Register Configuration Table 9-2 lists the SCI registers. Table 9-2. SCI Registers Channel Name 0 Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register ...
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Receive Data Register (RDR) – H’FFDD Bit 7 Initial value 0 Read/Write R The RDR stores received data. As each character is received transferred from the RSR to the RDR, enabling the RSR to receive the next ...
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Serial Mode Register (SMR) – H’FFD8 Bit 7 C/A Initial value 0 Read/Write R/W The SMR is an 8-bit readable/writable register that controls the communication format and selects the clock rate for the internal clock source initialized ...
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Bit 4 – Parity Mode (O asynchronous mode, when parity is enabled (PE = 1), this bit selects even or odd parity. Even parity means that a parity bit is added to the data bits for each character ...
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Serial Control Register (SCR) – H’FFDA Bit 7 TIE Initial value 0 Read/Write R/W The SCR is an 8-bit readable/writable register that enables or disables various SCI functions initialized to H’ reset and in the ...
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Bit 4 – Receive Enable (RE): This bit enables or disables the receive function. When the receive function is enabled, the RxD pin is automatically used for input. When the receive function is disabled, the RxD pin is available as ...
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Serial Status Register (SSR) – H’FFDC Bit 7 TDRE Initial value 1 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* * Software can write clear the flags, but cannot write these bits. The SSR is ...
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Bit 5 – Overrun Error (ORER): This bit indicates an overrun error during reception. Bit 5 ORER Description 0 To clear ORER, the CPU must read ORER after it has been set to 1, then write this ...
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Bit Rate Register (BRR) – H’FFD9 Bit 7 Initial value 1 Read/Write R/W The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines the baud rate output by the baud rate ...
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Table 9-3. Examples of BRR Settings in Asynchronous Mode (2) 4.9152 Bit Error rate n N (%) 110 1 174 –0.26 150 1 127 0 300 0 255 0 600 0 127 0 1200 2400 0 31 ...
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Table 9-3. Examples of BRR Settings in Asynchronous Mode (4) 14.7456 Bit Error rate n N (%) 110 2 130 –0.07 150 300 1 191 0 600 1200 0 191 0 2400 0 95 ...
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Table 9-4. Examples of BRR Settings in Synchronous Mode Bit 2 4 rate 100 — — — 250 1 249 2 500 1 124 249 1 2. ...
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Operation 9.3.1 Overview The SCI supports serial data transfer in both asynchronous and synchronous modes. The communication format depends on settings in the SMR as indicated in table 9-5. The clock source and usage of the SCK pin depend ...
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Transmitting and receiving operations in the two modes are described next. 9.3.2 Asynchronous Mode In asynchronous mode, each character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the ...
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Table 9-7. Data Formats in Asynchronous Mode SMR bits CHR PE STOP Note START: Start bit ...
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Data Transmission and Reception • SCI Initialization: Before data can be transmitted or received, the SCI must be initialized by software. To initialize the SCI, software must clear the TE and RE bits to 0, then execute the following ...
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The first byte of transmit data is transferred from the TDR to the TSR and sent in the designated format as follows. i) Start bit (one 0 bit). ii) Transmit data (seven or eight bits, starting from bit 0) iii) ...
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If a receive error occurs, the RDRF bit in the SSR is not set to 1. (For an overrun error, RDRF is already set to 1.) The corresponding error flag is set to 1 instead. If the RIE bit in ...
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Serial clock Data Bit 0 Don’t-care Figure 9-4. Data Format in Synchronous Mode (2) Clock: Either the internal serial clock created by the on-chip baud rate generator or an external clock input at the SCK pin can be selected in ...
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When clearing the TDRE bit during data transmission, to assure correct data transfer, do not clear the TDRE bit until after writing data in the TDR. Similarly, in receiving data, do not clear the RDRF bit until after reading data ...
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Set up the desired receiving conditions in the SMR, BRR, and SCR. Set the RE bit in the SCR to 1. The RxD pin is automatically be switched to input and the SCI is ready to receive data. Incoming data ...
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Data transmitting and receiving start when the TDRE bit in the SSR is cleared to 0. Data are sent and received in synchronization with eight clock pulses. First, the transmit data are transferred from the TDR to the TSR. This ...
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Table 9-9. SCI Interrupts Interrupt Description ERI Receive-error interrupt, requested when ORER, FER, or PER is set. RIE must also be set. RXI Receive-end interrupt, requested when RDRF and RIE are set. TXI Transmit-end interrupt, requested when TDRE and TIE ...