M30800SAGP#D5 Renesas Electronics America, M30800SAGP#D5 Datasheet - Page 14
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M30800SAGP#D5
Manufacturer Part Number
M30800SAGP#D5
Description
IC M16C MPU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAFPU5.pdf
(62 pages)
Specifications of M30800SAGP#D5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30800SAGP#D5M30800SAGP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30800SAGP#D5M30800SAGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
M30800SAGP#D5M30800SAGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
R
2. Central Processing Unit (CPU)
e
E
3
. v
J
2
Figure 2.1 CPU Register
0
C
Figure 2.1 shows the CPU registers.
The register bank is comprised of 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers.
Two sets of register banks are provided.
1
3
1 .
8 /
B
0
0
0
0
3
G
N
8
o
o r
0 -
. v
u
1
General Registers
High-speed Interrupt Registers
DMAC-associated Registers
0
p
1
NOTE:
, 1
0
1. The register bank is comprised of these registers. Two sets of register banks are provided.
2
0
0
5
Page 12
b31
b15
f o
5
6
IPL
R2
R3
b23
b23
b23
b8
b15
b15
b15
b7
U I O B S Z D C
DMA0
DMA1
DRA0
DRA1
DSA0
DSA1
INTB
R0H
R1H
USP
SVP
VCT
ISP
PC
A0
A1
SB
FB
DRC0
DRC1
DCT0
DCT1
SVF
FLG
R2
R3
b7
DMD0
DMD1
R0L
R1L
b0
b0
b0
b0
Data Register
Address Register
Static Base Register
Frame Base Register
User Stack Pointer
Interrupt Stack Pointer
Interrupt Table Register
Program Counter
Flag Save Register
PC Save Register
Vector Register
DMA Mode Register
DMA Transfer Count Register
DMA Transfer Count Reload Register
DMA Memory Address Register
DMA Memory Address Reload Register
DMA SFR Address Register
Flag Register
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Space
Processor Interrupt Priority Level
Reserved Space
2. Central Processing Unit (CPU)
(1)
(1)
(1)
(1)