M30833FJGP#D5 Renesas Electronics America, M30833FJGP#D5 Datasheet - Page 54

• Manufacturer Part Number: M30833FJGP#D5
• Description: IC M32C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#D5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

R
R
M
e
E
. v
3
J
Switching Characteristics
(V
Table 5.21 Memory Expansion Mode and Microprocessor Mode
0
2
N
d t
h t
h t
h t
d t
h t
h t
h t
d t
h t
d t
h t
d t
h t
d t
h t
w t
1
3
C
O
S
B (
B (
R (
(
B (
B (
R (
(
B (
B (
B (
B (
B (
B (
D (
(
4 .
CC
B
W
W
W
(
W
8 /
y
C
C
D
C
C
D
C
C
C
C
C
- B
T
C
. 1
t
t
t
t
t
R
R
R
) R
0
1
L
L
A -
L
L
C -
L
L
L
L
L
d(DB – WR)
h(WR – DB)
h(WR – AD)
h(WR – CS)
w( WR)
m
A -
C -
W
D -
L
E
K
K
K
K
K
K
K
K
- K
0
- K
3
) D
) S
= 4.2 to 5.5V, V
A -
A -
) D
C -
C -
A -
A -
R -
R -
) R
) S
) B
V
: S
b
W
1
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a
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3
a
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)
n
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3 .
=
s
1
R
R
D
D
A
A
A
A
C
C
C
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A
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W
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u
, 1
4
d
d
d
d
L
L
D
D
a
a
c
h
h
h
h
p
R
R
R
1
a
d
d
d
d
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E
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a t
p i
p i
p i
p i
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=
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S
S
n
2
e r
e r
e r
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S
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(With a Wait State, Accessing an External Memory)
s -
s -
s -
s -
S
S
0
M
g i
g i
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b
s s
s s
s s
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g i
u
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g i
g i
0
f
e
10 X n
n
n
u
u
p t
f
(BCLK)
3
e l
e l
e l
e l
n
n
10 X n
6
n
n
f
f
f
l a
l a
p t
p t
(BCLK)
o
(BCLK)
(BCLK)
(BCLK)
O
O
O
O
l a
l a
2
t u
t c
t c
t c
t c
l a
l a
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9
t u
t u
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u
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9
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p t
p t
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p t
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10
10
10
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u
Page 52
8 /
D
H
u
u
n i
SS
g i
g i
g i
g i
u
u
p t
p t
t u
t u
t u
t u
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p t
p t
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o
X 2
p t
p t
e
, 3
n
n
n
n
9
9
9
t u
t u
a l
d l
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X 2
X 2
X 2
d
D
H
H
H
t u
t u
l a
l a
l a
l a
t u
t u
= 0V at Topr = –20 to 85
y
e
o
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i T
M
D
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f
– 20
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H
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d l
d l
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D
H
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3
u
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– 15
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a l
d l
m
i T
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d l
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p t
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p t
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2
a l
d l
P
– 10
– 10
– 10
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m
m
m
C
t u
t u
t u
t u
(
f o
a
y
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W
m
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a r
m
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8 /
W
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m
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m
m
9
R
m
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m
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B (
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m
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t e
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a l
d l
d l
d l
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e
C
D
s
a t
R
r e
[ns] (n=1 with 1 wait state, n=2 with 2 wait states
[ns]
[ns]
[ns]
[ns] (n=1 with 1 wait state, n=3 with 2 wait states
y
L
a t
w
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i T
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n
s
K
s
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n
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m
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r a
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m
g
n
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n
r a
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d
e
) d
e
d
and n=3 with 3 wait states)
and n=5 with 3 wait states)
B (
(
(
r a
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n
q
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r a
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C
D
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a t
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s
n
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n
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d
d
n
r a
a
r a
o
d
c c
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r a
) d
o
) d
d r
n i
g
See Figure 5.1
M
o t
e
C
B
a
o
C
s
n
u
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d
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K
t i
m
o i
f
e r
n
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t n
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e
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c
(
(
(
(
(
. y
N
N
N
N
N
M
o
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o
3 -
3 -
2 -
5 -
3 -
0
0
e t
e t
e t
e t
e t
n i
S
) 1
) 1
) 1
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a t
n
d
a
d r
M
1
1
1
1
1
a
8
8
8
8
8
x
U
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
t i
V
CC
=5V