MC9S08GT16CFDE Freescale Semiconductor, MC9S08GT16CFDE Datasheet - Page 93
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MC9S08GT16CFDE
Manufacturer Part Number
MC9S08GT16CFDE
Description
IC MCU 16K FLASH 20MHZ 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.M68EVB908GB60E.pdf
(290 pages)
Specifications of MC9S08GT16CFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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PTFPEn — Pullup Enable for Port F Bit n (n = 0–7)
PTFSEn — Slew Rate Control Enable for Port F Bit n (n = 0–7)
PTFDDn — Data Direction for Port F Bit n (n = 0–7)
6.6.7
Port G includes eight general-purpose I/O pins that are shared with BKGD/MS function and the oscillator
or external clock pins. Port G pins used as general-purpose I/O pins are controlled by the port G data
(PTGD), data direction (PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers.
Port pin PTG0, while in reset, defaults to the BKGD/MS pin. After the MCU is out of reset, PTG0 can be
configured to be a general-purpose output pin. When BKGD/MS takes control of PTG0, the corresponding
PTGDD, PTGPE, and PTGPSE bits are ignored.
Port pins PTG1 and PTG2 can be configured to be oscillator or external clock pins. When the oscillator
takes control of a port G pin, the corresponding PTGD, PTGDD, PTGSE, and PTGPE bits are ignored.
Reads of PTGD will return the logic value of the corresponding pin, provided PTGDD is 0.
Freescale Semiconductor
For port F pins that are inputs, these read/write control bits determine whether internal pullup devices
are enabled. For port F pins that are configured as outputs, these bits are ignored and the internal pullup
devices are disabled.
For port F pins that are outputs, these read/write control bits determine whether the slew rate controlled
outputs are enabled. For port F pins that are configured as inputs, these bits are ignored.
These read/write bits control the direction of port F pins and what is read for PTFD reads.
1 = Internal pullup device enabled.
0 = Internal pullup device disabled.
1 = Slew rate control enabled.
0 = Slew rate control disabled.
1 = Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.
0 = Input (output driver disabled) and reads return the pin value.
Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD)
MC9S08GB/GT Data Sheet, Rev. 2.3
Parallel I/O Registers and Control Bits
93
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