MC908GR32AMFAE Freescale Semiconductor, MC908GR32AMFAE Datasheet - Page 199

• Manufacturer Part Number: MC908GR32AMFAE
• Description: IC MCU 8BIT 32K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR32AMFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.7 SIM Registers
The SIM has three memory-mapped registers.
14.7.1 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
SBSW — SIM Break Stop/Wait
14.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status bits
have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit
and clears all other bits in the register.
The register is initialized on power up with the POR bit set and all other bits cleared. During a POR or any
other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32 CGMXCLK
cycles later. If the pin is not above V
other bits are set.
Freescale Semiconductor
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
$FE00
$FE01
POR
Bit 7
Bit 7
R
R
0
1
Figure 14-22. SIM Reset Status Register (SRSR)
Address
$FE00
$FE01
$FE03
Figure 14-21. Break Status Register (BSR)
= Unimplemented
= Reserved
PIN
R
6
0
6
0
IH
Table 14-4. SIM Registers
at this time, then the PIN bit may be set, in addition to whatever
COP
R
5
0
5
0
Register
SRSR
BFCR
BSR
Table 14-4
1. Writing a 0 clears SBSW.
ILOP
R
4
0
4
0
shows the mapping of these registers.
ILAD
R
3
0
3
0
Access Mode
MODRST
User
User
User
R
2
0
2
0
Note
SBSW
LVI
1
0
1
0
(1)
Bit 0
Bit 0
R
0
0
0
SIM Registers
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