MC908GR60AMFAE Freescale Semiconductor, MC908GR60AMFAE Datasheet - Page 204
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MC908GR60AMFAE
Manufacturer Part Number
MC908GR60AMFAE
Description
IC MCU 8BIT 60K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR60AMFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR60AMFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Serial Peripheral Interface (SPI) Module
15.3.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. See
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control
register with SPRF set and then reading the SPI data register. Writing to the SPI data register (SPDR)
clears SPTE.
15.3.2 Slave Mode
The SPI operates in slave mode when SPMSTR is clear. In slave mode, the SPSCK pin is the input for
the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must
be low. SS must remain low until the transmission is complete. See
In a slave SPI module, data enters the shift register under the control of the serial clock from the master
SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register,
and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data
register before another full byte enters the shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is
twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for
204
15.12.2 SPI Status and Control
In a multi-SPI system, configure the SPI modules as master or slave before
enabling them. Enable the master SPI before enabling the slave SPI.
Disable the slave SPI before disabling the master SPI. See
Control
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
SHIFT REGISTER
GENERATOR
MASTER MCU
BAUD RATE
Register.
Figure 15-4. Full-Duplex Master-Slave Connections
Register.) Through the SPSCK pin, the baud rate generator of the
MISO
MOSI
SPSCK
SS
Figure
NOTE
V
15-4.
DD
SPSCK
MISO
MOSI
SS
15.6.2 Mode Fault
SHIFT REGISTER
15.12.1 SPI
SLAVE MCU
Freescale Semiconductor
Error.
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