M30803FGFP#D5 Renesas Electronics America, M30803FGFP#D5 Datasheet - Page 64
M30803FGFP#D5
Manufacturer Part Number
M30803FGFP#D5
Description
MCU 3/5V 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet
1.M30803FGGPU3.pdf
(360 pages)
Specifications of M30803FGFP#D5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M
R
R
8.6 Status Transition of BCLK
e
E
1
v
J
6
1 .
0
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 8.6 shows the operating modes corresponding to the settings of system clock control regis-
ters 0 and main clock division register.
After a reset, operation defaults to division by 8 mode. When shifting to stop mode, reset or stopping main
clock, the main clock division register (address 000C
(1) Division by 2 mode
(2) Division by 3 mode
(3) Division by 4 mode
(4) Division by 6 mode
(5) Division by 8 mode
(6) Division by 10 mode
(7) Division by 12 mode
(8) Division by 14 mode
(9) Division by 16 mode
(10) No-division mode
(11) Low-speed mode
(12) Low power dissipation mode
C
9
0 .
8 /
The main clock is divided by 2 to obtain the BCLK.
The main clock is divided by 3 to obtain the BCLK.
The main clock is divided by 4 to obtain the BCLK.
The main clock is divided by 6 to obtain the BCLK.
The main clock is divided by 8 to obtain the BCLK. After reset, this mode is executed. Note that oscillation
of the main clock must have stabilized before transferring from this mode to no-division, division by 2, 6,
10, 12, 14 and 16 mode.
Oscillation of the sub clock must have stabilized before transferring to low-speed and low power dissipa-
tion mode.
The main clock is divided by 10 to obtain the BCLK.
The main clock is divided by 12 to obtain the BCLK.
The main clock is divided by 14 to obtain the BCLK.
The main clock is divided by 16 to obtain the BCLK.
The main clock is divided by 1 to obtain the BCLK.
f
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
f
When the main clock is stoped, the main clock division register (address 000C
8 mode.
B
C
C
0
0
0
is the BCLK and the main clock is stopped.
1
is used as BCLK. Note that oscillation of both the main and sub clocks must have stabilized before
A
G
8
u
7
o r
. g
0 -
u
1
0
p
0
, 2
0
2
0
0
5
Page 51
f o
3
2
9
16
) is set to “08
16
”.
8. Clock Generating Circuit
16
) is set to the division by
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