MC9S12XD256VAG Freescale Semiconductor, MC9S12XD256VAG Datasheet - Page 859
MC9S12XD256VAG
Manufacturer Part Number
MC9S12XD256VAG
Description
IC MCU 256K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of MC9S12XD256VAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
14K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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22.3.2.46 Port H Data Register (PTH)
Read: Anytime.
Write: Anytime.
Port H pins 7–0 are associated with the SCI4 and SCI5 as well as the routed SPI1 and SPI2 modules.
These pins can be used as general purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
The routed SPI2 function takes precedence over the SCI4 and SCI5 and the general purpose I/O function
if the routed SPI2 module is enabled. Refer to SPI section for details.
The routed SPI1 function takes precedence over the general purpose I/O function if the routed SPI1 is
enabled. Refer to SPI section for details.
The SCI4 and SCI5 function takes precedence over the general purpose I/O function if the SCI4 or SCI5
is enabled. Refer to SCI section for details.
Freescale Semiconductor
Routed
Reset
SPI
W
R
PTH7
SS2
0
7
SCK2
PTH6
0
6
Figure 22-48. Port H Data Register (PTH)
MOSI2
MC9S12XDP512 Data Sheet, Rev. 2.21
PTH5
0
5
MISO2
PTH4
0
4
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
PTH3
SS1
0
3
SCK1
PTH2
0
2
MOSI1
PTH1
0
1
MISO1
PTH0
0
0
861
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