C8051F537-IM Silicon Laboratories Inc, C8051F537-IM Datasheet - Page 146
![IC 8051 MCU 2K FLASH 20QFN](/photos/12/25/122567/silicon_laboratories_inc-20-qfn_sml.jpg)
C8051F537-IM
Manufacturer Part Number
C8051F537-IM
Description
IC 8051 MCU 2K FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F53xr
Specifications of C8051F537-IM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.25 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-QFN
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1400
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F537-IM
Manufacturer:
Silicon Labs
Quantity:
135
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C8051F52x/F52xA/F53x/F53xA
15.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma-
ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg-
ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
MARK
START
STOP
D0
D1
D2
D3
D4
D5
D6
D7
D8
BIT
BIT
SPACE
BIT TIMES
BIT SAMPLING
Figure 15.5. 9-Bit UART Timing Diagram
146
Rev. 1.3
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