C8051F537-IT Silicon Laboratories Inc, C8051F537-IT Datasheet - Page 157
![IC 8051 MCU 2K FLASH 20TSSOP](/photos/12/46/124608/silicon_laboratories_inc-20-tssop_sml.jpg)
C8051F537-IT
Manufacturer Part Number
C8051F537-IT
Description
IC 8051 MCU 2K FLASH 20TSSOP
Manufacturer
Silicon Laboratories Inc
Series
C8051F53xr
Specifications of C8051F537-IT
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.25 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
336-1401
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F537-IT
Manufacturer:
Silicon Labs
Quantity:
135
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SFR Definition 16.2. SPI0CN: SPI0 Control
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–2: NSSMD1–NSSMD0: Slave Select Mode.
Bit1:
Bit0:
SPIF
R/W
Bit7
SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not
automatically cleared by hardware. It must be cleared by software.
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) if a write to SPI0DAT is
attempted when the transmit buffer has not been emptied to the SPI shift register. When this
occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written. This
bit is not automatically cleared by hardware. It must be cleared by software.
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode
collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not auto-
matically cleared by hardware. It must be cleared by software.
RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buf-
fer still holds unread data from a previous transfer and the last bit of the current transfer is
shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must
be cleared by software.
Selects between the following NSS operation modes:
(See Section “16.2. SPI0 Master Mode Operation” on page 152 and Section “16.3. SPI0
Slave Mode Operation” on page 153).
00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will
assume the value of NSSMD0.
TXBMT: Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When
data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1,
indicating that it is safe to write a new byte to the transmit buffer.
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
WCOL
R/W
Bit6
MODF
R/W
Bit5
RXOVRN NSSMD1 NSSMD0
R/W
Bit4
C8051F52x/F52xA/F53x/F53xA
Rev. 1.3
R/W
Bit3
R/W
Bit2
TXBMT
Bit1
R
SFR Address: 0xF8
SPIEN
R/W
Bit0
00000110
Addressable
Reset Value
Bit
157
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