MC9S08DV32MLF Freescale Semiconductor, MC9S08DV32MLF Datasheet - Page 148
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MC9S08DV32MLF
Manufacturer Part Number
MC9S08DV32MLF
Description
IC MCU 32K FLASH 2K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV32MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV32MLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
In bypassed low power external mode, the MCGOUT clock is derived from the external reference clock.
The external reference clock which is enabled can be an external crystal/resonator or it can be another
external clock source.
The PLL and the FLL are disabled at all times in BLPE mode and the MCGLCLK will not be available
for BDC communications. If the BDM becomes active the mode will switch to one of the bypassed
external modes as determined by the state of the PLLS bit.
8.4.1.9
Stop mode is entered whenever the MCU enters a STOP state. In this mode, the FLL and PLL are disabled
and all MCG clock signals are static except in the following cases:
MCGIRCLK will be active in stop mode when all the following conditions occur:
MCGERCLK will be active in stop mode when all the following conditions occur:
8.4.2
When switching between engaged internal and engaged external modes the IREFS bit can be changed at
anytime, but the RDIV bits must be changed simultaneously so that the reference frequency stays in the
range required by the state of the PLLS bit (31.25 kHz to 39.0625 kHz if the FLL is selected, or 1 MHz to
2 MHz if the PLL is selected). After a change in the IREFS value the FLL or PLL will begin locking again
after the switch is completed. The completion of the switch is shown by the IREFST bit .
For the special case of entering stop mode immediately after switching to FBE mode, if the external clock
and the internal clock are disabled in stop mode, (EREFSTEN = 0 and IREFSTEN = 0), it is necessary to
allow 100us after the IREFST bit is cleared to allow the internal reference to shutdown. For most cases the
delay due to instruction execution times will be sufficient.
The CLKS bits can also be changed at anytime, but in order for the MCGLCLK to be configured correctly
the RDIV bits must be changed simultaneously so that the reference frequency stays in the range required
by the state of the PLLS bit (31.25 kHz to 39.0625 kHz if the FLL is selected, or 1 MHz to 2MHz if the
PLL is selected). The actual switch to the newly selected clock will be shown by the CLKST bits. If the
newly selected clock is not available, the previous clock will remain selected.
For details see
148
•
•
•
•
•
•
LP bit is written to 1
BDM mode is not active
IRCLKEN = 1
IREFSTEN = 1
ERCLKEN = 1
EREFSTEN = 1
Mode Switching
Stop
Figure
8-8.
MC9S08DV60 Series Data Sheet, Rev 3
Freescale Semiconductor
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