MCF54455CVR200 Freescale Semiconductor, MCF54455CVR200 Datasheet - Page 46

• Manufacturer Part Number: MCF54455CVR200
• Description: IC MPU 32BIT 200MHZ 360TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF5445xr

Specifications of MCF54455CVR200

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 132
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 360-TEPBGA
• Processor Series: MCF544x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 16 KB
• Data Ram Size: 32 KB
• Interface Type: I2C, SPI, SSI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M54455EVB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 16 Channel
• On-chip Dac: 16 bit, 16 Channel
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• For Use With: M54455EVB - BOARD EVAL FOR MCF5445X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision History
9
Table 34
46
Rev. No.
0
1
2
3
4
5
6
summarizes revisions to this document.
Revision History
Sept 17, 2007 Initial public release.
Feb 15, 2008 Corrected VSS pin locations in MCF5445x signal information and muxing table for the 360 TEPBGA
Apr 12, 2009 Rescinded previous errata, the 256-pin devices do not contain the PCI bus controller:
Apr 27, 2009 In
Oct 15, 2009 In
May 1, 2008 In Family Configurations table, added PCI as feature on 256-pin devices. On these devices the
Dec 1, 2008 Changed “360PBGA” heading to “360 TEPBGA” in
Date
Updated FlexBus read and write timing diagrams and added two notes before them.
Change FB_A[23:0] to FB_A[31:0] in FlexBus read and write timing diagrams.
Added power consumption section.
In Absolute Maximum Ratings table, changed RTCV
In DC Electrical Specifications table:
Changed the following specs in
• Changed RTCV
• Changed High Impedance (Off-State) Leakage Current (I
• Minimum frequency of operation from — to 60MHz
• Maximum clock period from — to 16.67 ns
• In
• In
Table 2
Table 8
package: changed “...M9, M16, M17...” to “...M9–M14, M16...”
PCI_AD bus is limited to 24-bits.
+2.0”.
added footnote to this spec: “Worst-case tristate leakage current with only one I/O pin high. Since
all I/Os share power when high, the leakage current is distributed among them. With all I/Os high,
this spec reduces to ±2 μA min/max.“
signals shown as — for 256-pin devices.
from “0
Table
Figure
MCF5445x ColdFire
°
changed MCF54450VM180 to MCF54450CVM180 and changed it’s temperature entry
changed Input Leakage Current (I
4, in PCI_ADn signal section, added a separate row for each package, with PCI_ADn
to +70
5, changed the PCI_ADn pins to their alternative function, FB_An.
°
DD
C” to “–40
Table 34. Revision History
specification from 3.0–3.6 to 1.35–1.65.
®
Microprocessor Data Sheet, Rev. 6
°
to +85
Table
Summary of Changes
13:
°
C”
in
) from ±1.0 to ±2.5μA
Table
DD
specification from “-0.3 to +4.0” to “-0.5 to
6.
OZ
) specification from ±1 to ±10μA, and
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