MPC5553MZP132 Freescale Semiconductor, MPC5553MZP132 Datasheet

IC MCU MPC5553 REV A 416-PBGA

MPC5553MZP132

Manufacturer Part Number
MPC5553MZP132
Description
IC MCU MPC5553 REV A 416-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC55xx Qorivvar
Datasheet

Specifications of MPC5553MZP132

Core Processor
e200z6
Core Size
32-Bit
Speed
132MHz
Connectivity
CAN, EBI/EMI, Ethernet, SCI, SPI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
220
Program Memory Size
1.5MB (1.5M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.65 V
Data Converters
A/D 40x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
416-PBGA
Processor Series
MPC5xxx
Core
e200z6
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
7-Wire, DSPI, ESCI
Maximum Clock Frequency
132 MHz
Number Of Timers
56
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
MPC5553EVBISYS - KIT EVAL ISYSTEMS MPC5553MPC5553EVBGHS - KIT EVAL GREEN HILLS SOFTWAREMPC5553EVB - KIT EVAL MPC5553MZP132MPC5553EVBE - BOARD EVAL FOR MPC5553
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC5553MZP132
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
Data Sheet: Technical Data
MPC5553
Microcontroller Data Sheet
by: Microcontroller Division
This document provides electrical specifications, pin
assignments, and package diagrams for the MPC5553
microcontroller device. For functional characteristics,
refer to the MPC5553/MPC5554 Microcontroller
Reference Manual.
1
The MPC5553 microcontroller (MCU) is a member of
the MPC5500 family of microcontrollers built on the
Power Architecture™ embedded technology. This
family of parts has many new features coupled with high
performance CMOS technology to provide substantial
reduction of cost per feature and significant performance
improvement over the MPC500 family.
The host processor core of this device complies with the
Power Architecture embedded category that is 100%
user-mode compatible (including floating point library)
with the original Power PC™ user instruction set
architecture (UISA). The embedded architecture
enhancements improve the performance in embedded
applications. The core also has additional instructions,
including digital signal processing (DSP) instructions,
beyond the original Power PC instruction set.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Overview
1
2
3
4
5
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22
3.11 H7Fa Flash Memory Electrical
3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14 Fast Ethernet Controller Specifications . . . . . . . . . 45
4.1
4.2
4.3
4.4
4.5
4.6
5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4
Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Revision History for the MPC5553 Data Sheet . . . . . . 60
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 6
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
EMI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9
ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9
VRC and POR Electrical Specifications . . . . . . . . 10
Power-Up/Down Sequencing . . . . . . . . . . . . . . . . 11
DC Electrical Specifications. . . . . . . . . . . . . . . . . . 13
Oscillator and FMPLL Electrical
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MPC5553 208 MAP BGA Pinout . . . . . . . . . . . . . . 49
MPC5553 324 PBGA Pinout . . . . . . . . . . . . . . . . 50
MPC5553 416 PBGA Pinout . . . . . . . . . . . . . . . . . 51
MPC5553 208-Pin Package Dimensions . . . . . . . 54
MPC5553 324-Pin Package Dimensions . . . . . . . 56
MPC5553 416-Pin Package Dimensions . . . . . . . 58
Information Changed Between Revisions
2.0 and 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Document Number: MPC5553
Contents
Rev. 3.0, 3 Jun 2008

Related parts for MPC5553MZP132

MPC5553MZP132 Summary of contents

Page 1

... The embedded architecture enhancements improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original Power PC instruction set. © Freescale Semiconductor, Inc., 2008. All rights reserved. Document Number: MPC5553 Rev. 3.0, 3 Jun 2008 Contents 1 Overview ...

Page 2

... MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs and DMA support. 2 MPC5553 Microcontroller Data Sheet, Rev. 3.0 Freescale Semiconductor ...

Page 3

... Figure 1. MPC5500 Family Part Number Example Unless noted in this data sheet, all specifications apply from T 1 Freescale Part Number MPC5553MVR132 MPC5553MVR112 MPC5553MVR80 MPC5553MVZ132 MPC5553MVZ112 MPC5553MVZ80 MPC5553MVM132 MPC5553MVM112 MPC5553MVM80 MPC5553MZP132 MPC5553MZP112 MPC5553MZP80 MPC5553MZQ132 MPC5553MZQ112 MPC5553MZQ80 Freescale Semiconductor M PC 5553 Qualification status Core code Device number Temperature range ...

Page 4

... DD33 V –0.3 4.6 RC33 V –0.3 5.5 DDA V –0.3 4.6 DDE V –0.3 6.5 DDEH –1.0 6.5 5 –1.0 4.6 V –0.3 5.5 RH – V –0.1 0.1 SS SSA – V – DDA DDA DD V – V –0.3 5 – V –5.5 5.5 RH DDA Freescale Semiconductor 2 Max 125° Unit ...

Page 5

... Total injection current for all pins (including both digital and analog) must not exceed 25 mA. 9 Total injection current for all analog input pins must not exceed 15 mA. 10 Lifetime operation at these specification limits is not guaranteed. 11 Moisture sensitivity profile per IPC/JEDEC J-STD-020D. 12 Moisture sensitivity per JEDEC test method A112. Freescale Semiconductor V V DDEH V Table 9 V SSSYN V ...

Page 6

... Table 3. MPC5553 Thermal Characteristics can be obtained from the equation: J × MPC5553 Microcontroller Data Sheet, Rev. 3.0 Packages Symbol 208 324 416 MAPBGA PBGA PBGA θ θ θJMA θJMA θ θJC Ψ C/W) Freescale Semiconductor Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W ...

Page 7

... R is device related and is not affected by other factors. The thermal environment can be controlled to θJC change the case-to-ambient thermal resistance, R add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal Freescale Semiconductor × C/W) per JESD51-8 θ ...

Page 8

... Applications,” Electronic Packaging and Production, pp. 53–58, March 1998. • Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220 determine the junction temperature by measuring the C/W) MPC5553 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 9

... Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature. Freescale Semiconductor for pinouts and package drawings. Table 4. EMI Testing Specifications Minimum 0 ...

Page 10

... TRANS_ON V 3.0 — VRC33REG 11.0 — 9.0 — VRCCTL 7.5 — V — 1.0 DD33_LAG — — — — BETA 55 500 DC Electrical Specifications. On power down, . must have a 20 μF (nominal) DD supply signals 2.2 V. VRCCTL Freescale Semiconductor Units V/ms — — — ...

Page 11

... V V DDE DD33 V V DDE DD33 Freescale Semiconductor DDSYN tied to ground (GND). To avoid power-sequencing, RC33 Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” must reach a certain voltage where the values are read as ones DD33 Section 3.7.1, “Input Value of Pins During POR Dependent on ...

Page 12

... V POR and the RESET DD MPC5553 Microcontroller Data Sheet, Rev. 3.0 Low Hi-Z is too low to correctly DD and V . DDE DDEH DD33 or RESET power pin (V DDSYN can lag V or the RESET power DDSYN lag specification DD33 power supply and the RESET DDSYN Freescale Semiconductor ) by DDEH6 ...

Page 13

... Fast I/O input low voltage 14 Medium and slow I/O input high voltage 15 Medium and slow I/O input low voltage 16 Fast input hysteresis Freescale Semiconductor 1.35 V and the RESET power reach 2.0 V DDSYN Figure 2. Power-Up Sequence (V Grounded) RC33 RC33 or the RESET power must decrease to less than 2.0 V before the V 1 MPC5553 Microcontroller Data Sheet, Rev ...

Page 14

... L — — C — — IN_A C — IN_M I — — — — — — — — — — — — DD Freescale Semiconductor Max. Unit V + 0.3 V DDA — V — DDE V DDEH DDEH 460 mA 360 mA 510 mA 410 mA 410 mA 310 mA 460 mA 370 mA 330 mA 225 ...

Page 15

... DDE7 V DDEH8 V DDEH9 14 31 Fast I/O weak pullup current 1.62–1.98 V 2.25–2.75 V 3.00–3.60 V Fast I/O weak pulldown current 1.62–1.98 V 2.25–2.75 V 3.00–3.60 V Freescale Semiconductor A 11 MHz MAX , MPC5553 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics = T – (continued) ...

Page 16

... V –50 RCVSS SS V – V –100 DDF DD – V –0.1 RC33 DDSYN V –2.5 IDIFF — — have a range of 1.6–3 EBTS = 1. DDE3 Freescale Semiconductor Max. Unit μA 150 μA 170 μA 2.5 2.0 mA 150 nA μA 2.5 100 mV + 0.1 V SSA 100 mV + 0 ...

Page 17

... Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 10. Freescale Semiconductor = 3.6 V and V = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. DDE DDEH ...

Page 18

... Freescale Semiconductor ...

Page 19

... These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input pins for the slow and medium pads only. 2 All loads are lumped. Freescale Semiconductor Current Specifications supply dependents on the usage of the pins on all I/O segments. The DD33 ...

Page 20

... DDE5 0.8 3 — 1.5 — 1.5 Refer to crystal Refer to crystal specification specification (2 × – S_EXTAL — 9 – C PCB_EXTAL (2 × – S_XTAL — 9 – C PCB_XTAL — 750 – –4.0 4.0 –2.0 2.0 Freescale Semiconductor Unit MHz MHz ns kHz MHz μ SYS % f SYS ...

Page 21

... Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod). 15 Modulation depth selected must not result in f ÷ RFD sys ico 17 Maximum value for dual controller (1:1) mode is (f Freescale Semiconductor = 3.0–3 0 SSSYN Symbol 13, 14 max: C SYS JITTER 15 C ...

Page 22

... The ADCLK ≥ V due to the presence of the sample RL SSA 9. DC Electrical Specifications, spec 35a) can Freescale Semiconductor Unit MHz ADCLK cycles μ Counts Counts Counts Counts Counts Counts mA Counts Counts ...

Page 23

... Data retention 2 Blocks with 0–1,000 P/E cycles Blocks with 1,001–100,000 P/E cycles 1 Typical endurance is evaluated at 25 information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for Nonvolatile Memory. Freescale Semiconductor Symbol 4 T dwprogram T pprogram T 16kpperase ...

Page 24

... V) DDE 4, 5 Rise / Fall Load Drive (ns) (pF 200 200 200 50 260 200 200 200 100 50 125 200 Freescale Semiconductor ...

Page 25

... These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at 1.35–1. 3.0–3 DDE 2 This parameter is supplied for reference and guaranteed by design (not tested). Freescale Semiconductor = 5 DDEH SRC / DSC Out Delay (binary) (ns) ...

Page 26

... To calculate the output delay with respect to the system clock, add a maximum of one Rising-edge Falling-edge out delay out delay Figure 4. Pad Output Delay Characteristic = MPC5553 Microcontroller Data Sheet, Rev. 3.0 ÷ Symbol Min. Max. Unit t 10 — t RPW CYC t 2 — t GPW CYC t 10 — t RCSU CYC t 0 — t RCH CYC Freescale Semiconductor ...

Page 27

... Boundary scan input valid to TCK rising-edge 15 TCK rising-edge to boundary scan input invalid 1 These specifications apply to JTAG boundary scan only. JTAG timing specified at: V Refer to Table 21 for Nexus specifications. Freescale Semiconductor 1 ÷ 2) DDE MPC5553 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics Symbol Min ...

Page 28

... Electrical Characteristics TCK 3 TCK TMS, TDI TDO 28 1 Figure 6. JTAG Test Clock Input Timing Figure 7. JTAG Test Access Port Timing MPC5553 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 29

... TCK JCOMP Freescale Semiconductor 9 Figure 8. JTAG JCOMP Timing MPC5553 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics 10 29 ...

Page 30

... Figure 9. JTAG Boundary Scan Timing Table 21. Nexus Debug Port Timing MPC5553 Microcontroller Data Sheet, Rev. 3 Symbol Min. Max MCYC MDC t –1.5 3.0 MDOV t –1.5 3.0 MSEOV t –1.5 3.0 EVTOV t 4.0 — EVTIPW t 1 — EVTOPW — TCYC TDC Freescale Semiconductor Unit t CYC % TCYC t MCYC t CYC % ...

Page 31

... Limit the maximum frequency to approximately 16 MHz (V specification for JOV JCYC 5 The RDY pin timing is asynchronous to MCKO and is guaranteed by design to function correctly. MCKO MDO MSEO EVTO Freescale Semiconductor t = 1.35–1. and with DSC = 0b10 2.25–3 MHz (V DDE ] as outlined in the IEEE-ISTO 5001-2003 specification. ...

Page 32

... Electrical Characteristics TCK TMS, TDI TDO Figure 11. Nexus TDI, TMS, TDO Timing MPC5553 Microcontroller Data Sheet, Rev. 3.0 12 Freescale Semiconductor ...

Page 33

... CAL_WE/BE[0:1] CLKOUT positive edge to output signal valid (output delay) External bus interface CS[0:3] ADDR[8:31] 5 DATA[0:31] 6 BDIP OE RD_WR TA 6 TEA TS 7 WE/BE[0:3] Freescale Semiconductor Table 22. Bus Operation Timing External Bus Frequency Symbol 40 MHz 56 MHz Min. Max. Min. Max. T 24.4 — 17 45% 55% ...

Page 34

... MPC5553 Microcontroller Data Sheet, Rev. 3.0 1 (continued Unit 66 MHz Max. Min. Max 8.5 7.0 ns EBTS = 0 — 9.5 8.0 EBTS = 1 Output valid time selectable via SIU_ECCR [EBTS] bit. — 5.0 — ns — 6.0 — ns — 1.0 — ns — 1.0 — and with DSC = 0b10 Freescale Semiconductor Notes ...

Page 35

... V DDE bus 5 Output ÷ DDE signal Output signal Freescale Semiconductor = 2.25–3.6 V only; EBTS = 1 timings are tested and valid at V DDE Voh_f 3 4 Figure 12. CLKOUT Timing 6 6 Figure 13. Synchronous Output Timing MPC5553 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics DDE ÷ ...

Page 36

... Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both. 36 ÷ DDE 7 ÷ DDE 7 Figure 14. Synchronous Input Timing Table 23. External Interrupt Timing Symbol t IPWL T IPWH t ICYC = MPC5553 Microcontroller Data Sheet, Rev. 3 Min. Max. Unit 3 — t CYC 3 — t CYC 6 — t CYC Freescale Semiconductor ...

Page 37

... This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). eTPU output eTPU input and TCRCLK Freescale Semiconductor 2 3 Figure 15. External Interrupt Timing Table 24. eTPU Timing = ...

Page 38

... MHz 132 MHz Min. Max. Min. Max. 17.5 ns 2.1 ms 15 — 13 — 14 — 12 — ÷ 2) ÷ 2) ÷ SCK SCK SCK SCK – – — 25 — 25 — 25 — — 4 — 5 — 5 — Freescale Semiconductor Unit t CYC t CYC Unit — ÷ ...

Page 39

... The actual minimum SCK cycle time is limited by pad performance. 5 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. 6 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. 7 This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10. Freescale Semiconductor 1 2 Table 26. DSPI Timing ’ (continued) 80 MHz Symbol Min ...

Page 40

... SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 19. DSPI Classic SPI Timing—Master, CPHA = Last data First data Data 12 First data Data Last data 9 Data First data 12 Data First data MPC5553 Microcontroller Data Sheet, Rev. 3 Last data 11 Last data Freescale Semiconductor ...

Page 41

... SCK input (CPOL=1) SOUT SIN Figure 20. DSPI Classic SPI Timing—Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 21. DSPI Classic SPI Timing—Slave, CPHA = 1 Freescale Semiconductor First data Data Last data 9 10 Data Last data First data ...

Page 42

... SCK output (CPOL=1) SIN SOUT Figure 23. DSPI Modified Transfer Format Timing—Master, CPHA = First data Last data Data 12 11 First data Last data Data 9 First data Data 12 First data Data MPC5553 Microcontroller Data Sheet, Rev. 3 Last data 11 Last data Freescale Semiconductor ...

Page 43

... SIN Figure 24. DSPI Modified Transfer Format Timing—Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 25. DSPI Modified Transfer Format Timing—Slave, CPHA = 1 PCSS PCSx Freescale Semiconductor First data Data Last data 10 9 Data First data Last data ...

Page 44

... Figure 27. EQADC SSI Timing MPC5553 Microcontroller Data Sheet, Rev. 3.0 Typical Maximum — × 6.5) — SYS_CLK 8 × 6.5) — SYS_CLK — +7.5 — +7.5 — — — — 4 25th 5 2nd 26th 25th 26th Freescale Semiconductor Unit t SYS_CLK ...

Page 45

... FEC_RX_CLK pulse-width low Figure 28 shows MII FEC receive signal timings listed in FEC_RX_CLK (input) FEC_RXD[3:0] (inputs) FEC_RX_DV FEC_RX_ER Figure 28. MII FEC Receive Signal Timing Diagram Freescale Semiconductor Table 28. MII FEC Receive Signal Timing Characteristic Table MPC5553 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics Min ...

Page 46

... FEC_TX_CLK (input) FEC_TXD[3:0] (outputs) FEC_TX_EN FEC_TX_ER Figure 29. MII FEC Transmit Signal Timing Diagram 46 Table 29. MII FEC Transmit Signal Timing Characteristic Table MPC5553 Microcontroller Data Sheet, Rev. 3.0 Min. Max Unit 5 — ns — 35% 65% FEC_TX_CLK period 35% 65% FEC_TX_CLK period 29. 8 Freescale Semiconductor ...

Page 47

... FEC_MDIO (input) to FEC_MDC rising-edge setup 13 FEC_MDIO (input) to FEC_MDC rising-edge hold 14 FEC_MDC pulse-width high 15 FEC_MDC pulse-width low Figure 31 shows MII FEC serial management channel timing listed in Freescale Semiconductor Characteristic 9 MPC5553 Microcontroller Data Sheet, Rev. 3.0 Electrical Characteristics Min. Max Unit 1.5 — ...

Page 48

... Electrical Characteristics FEC_MDC (output) FEC_MDIO (output) FEC_MDIO (input) Figure 31. MII FEC Serial Management Channel Timing Diagram MPC5553 Microcontroller Data Sheet, Rev. 3.0 15 Freescale Semiconductor ...

Page 49

... VSS VDD 3 2 207 GPIO EMIOS R CS0 VSS VDD 206 4 EMIOS EMIOS T VSS VDD Freescale Semiconductor NOTES are connected internally on the 208-ball package and . AN1 AN5 VRH VRL AN27 REF AN22 AN25 AN28 AN4 BYPC AN16 AN3 AN7 AN23 AN32 AN6 ...

Page 50

... CNTXA VDDE5 NC VSS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 Freescale Semiconductor 21 22 VDD33 VSS A VSS VDDE7 B VDDE7 VDD C TCK TDI D TDO TEST E EVTI EVTO F G GPIO SINB H 204 J K SINA SCKA L VPP ...

Page 51

... VDD DATA DATA DATA DATA GPIO AF VSS VDD VDDE2 206 Freescale Semiconductor show the pinout for the MPC5553 416 PBGA package. While the NOTE ETRIG VRH AN23 AN27 AN28 AN35 VSSA0 AN15 1 REF ETRIG AN22 AN26 AN31 AN32 VSSA0 AN14 BYPC ...

Page 52

... VDDE2 VDDE2 VSS VSS VDDE2 VDDE2 VSS VSS VDDE2 VDDE2 VSS VSS VDDE2 VSS VDDE2 VDDE2 VSS VDDE2 VDDE2 VDDE2 DATA DATA DATA DATA VDDE2 GPIO DATA DATA DATA VDD33 207 DATA DATA DATA DATA DATA DATA DATA VDDE2 Freescale Semiconductor ...

Page 53

... DATA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS NC_38 Figure 35. MPC5553 416 Package Right Side (view Freescale Semiconductor GPIO NC_2 NC_3 NC_4 MDO11 MDO8 205 NC_6 NC_7 NC_8 MDO10 MDO7 MDO9 MDO6 MDO3 VDDEH MDO5 MDO2 EMIOS EMIOS VDDEH ...

Page 54

... Mechanicals 4.4 MPC5553 208-Pin Package Dimensions The package drawings of the MPC5553 208-pin MAP BGA are shown in 54 Figure 36. MPC5553 208-Pin Package MPC5553 Microcontroller Data Sheet, Rev. 3.0 Figure 36. Freescale Semiconductor ...

Page 55

... Figure 36. MPC5553 208 MAP BGA Package (continued) Freescale Semiconductor MPC5553 Microcontroller Data Sheet, Rev. 3.0 Mechanicals 55 ...

Page 56

... Mechanicals 4.5 MPC5553 324-Pin Package Dimensions The package drawings of the MPC5553 324-pin TEPBGA package are shown in 56 Figure 37. MPC5553 324 TEPBGA Package MPC5553 Microcontroller Data Sheet, Rev. 3.0 Figure 37. Freescale Semiconductor ...

Page 57

... Figure 37. MPC5553 324 TEPBGA Package (continued) Freescale Semiconductor MPC5553 Microcontroller Data Sheet, Rev. 3.0 Mechanicals 57 ...

Page 58

... Mechanicals 4.6 MPC5553 416-Pin Package Dimensions The package drawings of the MPC5553 416 pin TEPBGA package are shown in 58 Figure 38. MPC5553 416 TEPBGA Package MPC5553 Microcontroller Data Sheet, Rev. 3.0 Figure 38. Freescale Semiconductor ...

Page 59

... Figure 38. MPC5553 416 TEPBGA Package (continued) Freescale Semiconductor MPC5553 Microcontroller Data Sheet, Rev. 3.0 Mechanicals 59 ...

Page 60

... Section 3.7.1, “Input Value of Pins During POR Dependent on • Section 3.7.2, “Power-Up Sequence (VRC33 • Section 3.7.3, “Power-Down Sequence (VRC33 60 Description of Change Table 1: ‘Unless noted in this data sheet, all specifications apply Grounded),” then Grounded). MPC5553 Microcontroller Data Sheet, Rev. 3.0 VDD33,” then Freescale Semiconductor ...

Page 61

... Reference Manual signals, the weak-pull devices can pull the signals avoid this condition, minimize the ramp time of the V enable the external circuitry connected to the device outputs.’ Freescale Semiconductor Description of Change VDD33,” changed: must not lag V ...

Page 62

... VRCCTL = 2.2 V.’ Changed ‘(@ Table 1 for the maximum operating frequency.’ ÷ VRCCTL MPC5553 Microcontroller Data Sheet, Rev. 3.0 ; the highest ambient L . MAX , V , and V POR15 POR33 Max 0.30 V Max 0. 1. )‘ to ‘(@ sys MAX sys MAX ). Freescale Semiconductor POR5 ...

Page 63

... Footnote 3 changed to read: If standby operation is not required, connect V • Footnote 6 is now: Figure 3 values. • Deleted footnote 9: ‘Preliminary. Final specification pending characterization.’ • Deleted duplicate footnote: ‘ Absolute value of current, measured at V Freescale Semiconductor Description of Changes and V are limited to 2.25–3.6 V only if EBTS = 0; V DDE2 DDE3 = – ...

Page 64

... SYS MAX to 20, and added footnote 17 to read, ‘Maximum value for MAX ÷ 2) and the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).’ MAX = T – the table title – the table title MPC5553 Microcontroller Data Sheet, Rev. 3 typical supply voltage using a Freescale Semiconductor ...

Page 65

... Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).’ Freescale Semiconductor Description of Changes Table 18 Derated Pad AC Specifications: The changes are identical in the tables. = 132 MHz.’ ...

Page 66

... DDEH DDEH = 1.35–1.65 V’ and ‘V and V DD DD33 DDSYN Specifications” : Figure 28, Figure 29, MPC5553 Microcontroller Data Sheet, Rev. 3.0 and V = 3.0–3.6 V’ and DD33 DDSYN = 3.0–3.6V.’ Figure 30, and Figure 31. Freescale Semiconductor ...

Page 67

... Freescale Semiconductor MPC5553 Microcontroller Data Sheet, Rev. 3.0 Revision History for the MPC5553 Data Sheet 67 ...

Page 68

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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