DS89C420-ENG Maxim Integrated Products, DS89C420-ENG Datasheet - Page 18
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DS89C420-ENG
Manufacturer Part Number
DS89C420-ENG
Description
IC MCU ULTRA 25MHZ HP 44-TQFP
Manufacturer
Maxim Integrated Products
Series
89Cr
Datasheet
1.DS89C420-QCS.pdf
(47 pages)
Specifications of DS89C420-ENG
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SIO, UART/USART
Peripherals
Power-Fail Reset, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS89C420-ENG
Manufacturer:
Maxim Integrated
Quantity:
10 000
Table 2. SFR Reset Value
MEMORY ORGANIZATION
There are three distinct memory areas in the DS89C420: scratchpad registers, program memory, and data
memory. All registers are located on-chip but the program and data memory spaces can either be on-chip, off-chip,
or both. There are 16kB of on-chip program memory implemented in flash memory and 1kB of on-chip data
memory space that can be configured as program space using the PRAME bit in the ROMSIZE feature. The
DS89C420 uses a memory-addressing scheme that separates program memory from data memory. The program
and data segments can be overlapped since they are accessed in different ways. If the maximum address of on-
chip program or data memory is exceeded, the DS89C420 performs an external memory access using the
expanded memory bus. The PSEN signal goes active-low to serve as a chip enable or output enable when
performing a code fetch from external program memory. MOVX instructions activate the RD or WR signal for
REGISTER
ROMSIZE
SADDR0
SADDR1
RCAP2H
SADEN0
SADEN1
STATUS
RCAP2L
WDCON
CKCON
CKMOD
T2MOD
SCON0
SCON1
T2CON
SBUF0
SBUF1
FCNTL
FDATA
PCON
TMOD
ACON
TCON
DPH1
DPL1
EXIF
PMR
PSW
EIP1
EIP0
DPH
DPS
ACC
DPL
TH0
TH1
TH2
TL0
TL1
TL2
EIE
IP1
IP0
SP
P0
P1
P2
P3
TA
IE
B
ADDR
AAh
BAh
CAh
CBh
CCh
CDh
8Ah
8Bh
8Ch
8Dh
8Eh
9Dh
A0h
A8h
A9h
B0h
B1h
B8h
B9h
C0h
C1h
C2h
C4h
C5h
C7h
C8h
C9h
D0h
D5h
D6h
D8h
E0h
E8h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
90h
91h
96h
98h
99h
F0h
F1h
F8h
BIT 7
0
0
0
0
0
0
0
1
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
Special
BIT 6
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
1
1
18 of 47
Special
BIT 5
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
1
Special
Special
BIT 4
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
Special
BIT 3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Special
Special
BIT 2
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Special
Special
BIT 1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0