DS87C550-QCL+ Maxim Integrated Products, DS87C550-QCL+ Datasheet - Page 10

• Manufacturer Part Number: DS87C550-QCL+
• Description: IC MCU EPROM ADC/PWM HS 68-PLCC
• Manufacturer: Maxim Integrated Products
• Series: 87Cr

Specifications of DS87C550-QCL+

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, PWM, WDT
• Number Of I /o: 55
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC, 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

MEMORY RESOURCES
As is convention within the 8051 architecture, the DS87C550 uses three memory areas. The total memory
configuration of the DS87C550 is 8kB of EPROM, 1kB of data SRAM and 256 bytes of scratchpad or
direct RAM. The 1kB of data space SRAM is read/write accessible and is memory mapped. This on-chip
SRAM is reached by the MOVX instruction. It is not used for executable memory. The scratchpad area is
256 bytes of register mapped RAM and is identical to the RAM found on the 80C52. There is no conflict
or overlap among the 256 bytes and the 1kB as they use different addressing modes and separate
instructions.
OPERATIONAL CONSIDERATION
The erasure window of the windowed CLCC package should be covered without regard to the
programmed/unprogrammed state of the EPROM. Otherwise, the device may not meet the AC and DC
parameters listed in the datasheet.
PROGRAM MEMORY
On-chip ROM begins at address 0000h and is contiguous through 1FFFh (8kB). Exceeding the maximum
address of on-chip ROM will cause the DS87C550 to access off-chip memory. However, the maximum
on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the
DS87C550 to behave like a device with less on-chip memory. This is beneficial when overlapping
external memory, such as Flash, is used.
With the ROMSIZE feature the maximum on-chip memory size is dynamically variable. Thus a portion
of on-chip memory can be removed from the memory map to access off-chip memory, then restored to
access on-chip memory. In fact, all of the on-chip memory can be removed from the memory map,
allowing the full 64kB memory space to be addressed as off-chip memory. ROM addresses that are larger
than the selected maximum are automatically fetched from outside the part via Ports 0 & 2. A depiction
of the ROM memory map is shown in Figure 2.
The ROMSIZE register is used to select the maximum on-chip decoded address for ROM. Bits RMS2,
RMS1, RMS0 (ROMSIZE2:0) have the following effect.
The reset default condition is a maximum on-chip ROM address of 8B. Thus no action is required if this
feature is not used. Therefore when accessing external program memory, the first 8kB would be
inaccessible. To select a smaller effective ROM size, software must alter bits RMS2-RMS0. Altering
these bits requires a Timed Access procedure as explained below. The ROMSIZE register should be
manipulated from a safe area in the program memory map. This is a program memory address that will
not be affected by the change. For example, do not select a maximum ROM size of 4kB from an internal
RMS2
0
0
0
0
1
1
1
1
RMS1
0
0
1
1
0
0
1
1
RMS0
0
1
0
1
0
1
0
1
Maximum on-chip
8kB (0h – 1FFFh)
4kB (0h - 0FFFh)
1kB (0h - 03FFh)
2kB (0h - 07FFh)
invalid - reserved
invalid - reserved
invalid - reserved
ROM Address
default
0k
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